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enif_alloc_env enif_get_local_pid enif_make_atom enif_send enif_free_env av_default_item_name cuda_load_resize cuda_resize_ptx call_resize_kernel cuTexObjectCreate cuTexObjectDestroy cuda_load_uyvy2yv12 cuda_load_argb_nv12 cuda_load_v210_nv12 cuda_call_uyvy2yv12 cuda_call_argb_nv12 cuda_call_v210_nv12 cuda_unload_func cuda_copy cuda_init cuCtxCreate_v2 cuda_error_reply cuCtxPopCurrent_v2 atm_ok cuCtxDestroy_v2 atm_error enif_make_int cuda_error_name cuda_get atm_deviceid atm_too_big enif_mutex_lock enif_mutex_unlock enif_make_tuple cuda_lock cuCtxPushCurrent_v2 cuda_unlock cuMemAllocPitch_v2 cuMemFree_v2 cuda_rgb_tex cuMemsetD2D8_v2 cuMemsetD2D16_v2 cuda_black_tex cu_copy_tex nvenc_check_encoder_param nvenc_check_cap atm_width option_error atm_height av_decode_video error_reply decode_resource enif_get_resource enif_inspect_binary enif_get_long av_packet_alloc av_packet_free av_malloc avcodec_send_packet av_free avcodec_receive_frame atm_undefined nvenc_decode_video realloc mp4_to_annexb enif_make_list enif_get_list_length enif_make_reverse_list cuvidParseVideoData cuvidMapVideoFrame64 cuvidUnmapVideoFrame64 av_strerror nvenc_init_decoder atm_config atm_h264 atm_mpeg2video atm_hevc atm_av1 atm_codec enif_is_map map_int atm_deinterlace try_map_int atm_dsurfaces atm_deinterlace_rate map_key atm_field atm_frame enif_priv_data calloc dlopen dlsym setup_worker enif_self cuvidDestroyVideoParser dlclose timeval_delta is_preset_present select_preset slow_preset ultrafast_preset medium_preset veryfast_preset fast_preset nvenc_select_preset atm_slow atm_medium atm_fast atm_veryfast atm_ultrafast nvenc_init_encoder enif_make_badarg nvenc_init_encode av_fifo_alloc2 encode_resource nvenc_encoder_free av_fifo_freep2 atm_bad_map map_size atm_b map_uint map_fps atm_input_pix_fmt map_string strcmp av_get_pix_fmt atm_pix_fmt atm_preset atm_profile nvenc_profile atm_level nvenc_level atm_gop atm_refs atm_bf atm_bframes atm_vmemcount try_map_uint atm_yadif try_map_qp_range atm_vbv_bufsize atm_rc_method atm_extra av_reduce nvenc_get_seq_params enif_alloc_binary enif_make_binary atm_true atm_false zero_copy_resource nvenc_encoder_alloc enif_make_new_map decode_destructor stop_worker avcodec_free_context encode_destructor nvenc_trans_free nvenc_logo_free nvenc_burn_free zero_copy_destructor nvenc_reconfigure_encoder nvenc_prepare_encoder_config nvenc_reconfigure_decoder nvenc_version load atm_bad_value atm_enomem atm_bad_option atm_string atm_debug atm_verbose atm_warning atm_info atm_fatal atm_panic atm_quiet atm_yuv atm_keyframe atm_full atm_decoder atm_encoder atm_mp2v atm_v210 atm_libx264 atm_mjpeg atm_mp2 atm_libx265 atm_pcm_mulaw atm_pcm_alaw atm_simple atm_baseline atm_main atm_main10 atm_high atm_bitrate atm_fps atm_num atm_den atm_align atm_subme atm_open_gop atm_interlace atm_temporal_tradeoff atm_qp_range atm_qpmini atm_qpmaxi atm_qpminp atm_qpmaxp atm_qpminb atm_qpmaxb atm_size atm_strategy atm_background atm_in_width atm_in_height atm_fit atm_fit_x atm_fit_y atm_fit_w atm_fit_h atm_fit_ratio atm_in_sar atm_sar atm_crop atm_left atm_top atm_resize_mode atm_uyvy422 atm_yuyv422 atm_argb atm_rgb48 atm_yuv420p atm_rc_max_rate atm_rc_min_rate atm_rc_buffer_size atm_filter_spec atm_look_ahead atm_win_brc_avg atm_win_brc_size atm_vbv_delay atm_input_channels atm_input_channel_layout atm_input_sample_rate atm_input_sample_fmt atm_channels atm_channel_layout atm_sample_rate atm_sample_fmt atm_async atm_air atm_filter atm_dthreads atm_zerocopy atm_tff atm_bff atm_tff_separated atm_bff_separated atm_vui_video_params atm_gen_pts atm_nvenc atm_lib_not_found atm_lib_not_load atm_driver_not_load atm_driver_version atm_no_permission atm_qsv_err_null atm_qsv_err_unsup atm_qsv_err_mem atm_qsv_err_not_enough atm_qsv_err_inval_handle atm_qsv_err_lock atm_qsv_err_not_init atm_qsv_err_aborted atm_qsv_err_device_lost atm_qsv_err_incompatible_param atm_qsv_err_inval_param atm_qsv_err_dev_failed atm_qsv_err_gpu_hang atm_qsv_wrn_incompatible_param atm_qsv_err_unknow atm_blur atm_yuv420p10 atm_hw_platform atm_dlopen atm_dlsym atm_instance atm_cuda atm_open_session atm_skip_frame atm_reconfigure atm_delta1 atm_delta2 atm_audio atm_unknown atm_$transcoder_log cuInit cuGetErrorName cuDeviceGetCount enif_mutex_create enif_open_resource_type cuDeviceGet cuDeviceGetName unload cuCtxSynchronize nif_init enif_make_list_cell enif_alloc_resource strcpy enif_release_resource strlen enif_make_resource_binary make_raw_video_frame nvenc_bitdepth_realloc nvenc_save_prev nvenc_trans_init nvenc_trans_upload nvenc_fps_delta nvenc_encoder_encode_frame av_fifo_write enc_queue_get_pending nvenc_encode_process_output nvenc_unmap av_fifo_read make_encoded_frame schedule_task term2str avcodec_find_decoder_by_name avcodec_alloc_context3 av_mallocz avcodec_open2 init_worker cuMemGetInfo_v2 enif_make_string enif_make_ulong enif_get_int nvenc_logo_init_bin strncpy nvenc_burn_init avfilter_graph_send_command nvenc_fps_free nvenc_fps_alloc av_rescale nvenc_fps_realloc cuda_crop cuda_resize enc_queue_get_avail nvenc_dyload_nvenc nvenc_map bin_to_bistream annexb_to_mp4 set_pic_params nvenc_logo nvenc_pad nvenc_burn av_expr_eval nvenc_h264_profile nvenc_hevc_profile nvenc_h264_level nvenc_hevc_level av_get_pix_fmt_string free_burn_graph avfilter_graph_free ff_load_image_bin av_image_copy_to_buffer av_expr_parse avfilter_graph_alloc avfilter_inout_alloc avfilter_get_by_name avfilter_graph_create_filter av_int_list_length_for_size av_opt_set_bin av_strdup avfilter_graph_parse_ptr avfilter_graph_config avfilter_inout_free av_frame_unref av_frame_get_buffer worker_loop enif_thread_exit enif_cond_wait enif_clear_env sprintf enif_cond_create enif_cond_destroy enif_thread_create enif_mutex_destroy enif_cond_broadcast enif_thread_join enif_make_copy enif_make_ref avfilter_graph_alloc_filter av_buffersrc_parameters_set avfilter_init_dict init_audio_graph av_channel_layout_default av_channel_layout_describe av_opt_set init_graph av_get_sample_fmt_name av_buffersink_set_frame_size init_graph_with_logo filter_frames av_load_logs enif_set_pid_undefined fetch_and_set_logger_pid atom_from_av_log_level nif_log_handler enif_is_pid_undefined log_callback_null av_log_get_level av_log_format_line stderr fputs set_enable_ffmpeg_logs ntohl avio_alloc_context avformat_alloc_context av_find_input_format avformat_open_input avformat_close_input avformat_find_stream_info avcodec_find_decoder av_read_frame av_frame_clone sws_getContext sws_freeContext sws_scale enif_make_long enif_get_map_value enif_get_uint map_bool enif_term_type enif_get_atom enif_get_string enif_get_ulong enif_get_double try_map_string map_dictionary enif_map_iterator_create enif_map_iterator_get_pair av_dict_set enif_map_iterator_next enif_map_iterator_destroy enif_get_tuple __bss_start _edata _end libavcodec.so.60 LIBAVCODEC_60 libavutil.so.58 LIBAVUTIL_58 libavfilter.so.9 LIBAVFILTER_9 libavformat.so.60 LIBAVFORMAT_60 libc.so.6 GLIBC_2.2.5 GLIBC_2.14 /opt/flussonic/lib/x86_64-linux-gnu libcuda.so.1 libnvcuvid.so.1 libnvidia-encode.so.1 x ` x x c x 5 x Q x N y j y N y P y - y S (y t h p p Б ʶ 0 0 @ 0 P l ` p + R В f @ ` 0 { P p - p i Г 6 գ X ` ` P X X 8{ @{ H{ P{ ( % x % % h % % % ` % { } ~ { | X | ~ 0 | { x| @ (~ `~ | | | x { { | 8| @} H} ~ 8 } ~ h } 8~ (} P ~ `{ ~ h } ~ @ 8 p
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// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-21554848
// Cuda compilation tools, release 8.0, V8.0.61
// Based on LLVM 3.4svn
//
.version 5.0
.target sm_20
.address_size 64
// .globl uint8_to_uint16
.visible .entry uint8_to_uint16(
.param .u64 uint8_to_uint16_param_0,
.param .u64 uint8_to_uint16_param_1,
.param .u64 uint8_to_uint16_param_2,
.param .u32 uint8_to_uint16_param_3,
.param .u32 uint8_to_uint16_param_4,
.param .u32 uint8_to_uint16_param_5
)
{
.reg .pred %p<4>;
.reg .b16 %rs<3>;
.reg .b32 %r<14>;
.reg .b64 %rd<13>;
ld.param.u64 %rd1, [uint8_to_uint16_param_0];
ld.param.u64 %rd2, [uint8_to_uint16_param_1];
ld.param.u64 %rd3, [uint8_to_uint16_param_2];
ld.param.u32 %r3, [uint8_to_uint16_param_3];
ld.param.u32 %r4, [uint8_to_uint16_param_4];
ld.param.u32 %r5, [uint8_to_uint16_param_5];
mov.u32 %r6, %ctaid.x;
mov.u32 %r7, %ntid.x;
mov.u32 %r8, %tid.x;
mad.lo.s32 %r1, %r7, %r6, %r8;
mov.u32 %r9, %ntid.y;
mov.u32 %r10, %ctaid.y;
mov.u32 %r11, %tid.y;
mad.lo.s32 %r2, %r9, %r10, %r11;
setp.ge.u32 %p1, %r2, %r5;
setp.ge.u32 %p2, %r1, %r4;
or.pred %p3, %p1, %p2;
@%p3 bra BB0_2;
cvta.to.global.u64 %rd4, %rd2;
shr.u32 %r12, %r3, 1;
mad.lo.s32 %r13, %r2, %r12, %r1;
mul.wide.u32 %rd5, %r13, 2;
add.s64 %rd6, %rd4, %rd5;
mov.u16 %rs1, 0;
st.global.u8 [%rd6], %rs1;
cvt.s64.s32 %rd7, %r2;
mul.lo.s64 %rd8, %rd7, %rd3;
cvt.s64.s32 %rd9, %r1;
add.s64 %rd10, %rd8, %rd9;
cvta.to.global.u64 %rd11, %rd1;
add.s64 %rd12, %rd11, %rd10;
ld.global.u8 %rs2, [%rd12];
st.global.u8 [%rd6+1], %rs2;
BB0_2:
ret;
}
// .globl uint16_to_uint8
.visible .entry uint16_to_uint8(
.param .u64 uint16_to_uint8_param_0,
.param .u64 uint16_to_uint8_param_1,
.param .u64 uint16_to_uint8_param_2,
.param .u64 uint16_to_uint8_param_3,
.param .u32 uint16_to_uint8_param_4,
.param .u32 uint16_to_uint8_param_5
)
{
.reg .pred %p<4>;
.reg .b16 %rs<2>;
.reg .b32 %r<13>;
.reg .b64 %rd<15>;
ld.param.u64 %rd1, [uint16_to_uint8_param_0];
ld.param.u64 %rd2, [uint16_to_uint8_param_1];
ld.param.u64 %rd3, [uint16_to_uint8_param_2];
ld.param.u64 %rd4, [uint16_to_uint8_param_3];
ld.param.u32 %r3, [uint16_to_uint8_param_4];
ld.param.u32 %r4, [uint16_to_uint8_param_5];
mov.u32 %r5, %ctaid.x;
mov.u32 %r6, %ntid.x;
mov.u32 %r7, %tid.x;
mad.lo.s32 %r1, %r6, %r5, %r7;
mov.u32 %r8, %ntid.y;
mov.u32 %r9, %ctaid.y;
mov.u32 %r10, %tid.y;
mad.lo.s32 %r2, %r8, %r9, %r10;
setp.ge.u32 %p1, %r2, %r4;
setp.ge.u32 %p2, %r1, %r3;
or.pred %p3, %p1, %p2;
@%p3 bra BB1_2;
cvta.to.global.u64 %rd5, %rd1;
shr.u64 %rd6, %rd3, 1;
cvt.u32.u64 %r11, %rd6;
mad.lo.s32 %r12, %r2, %r11, %r1;
mul.wide.u32 %rd7, %r12, 2;
add.s64 %rd8, %rd5, %rd7;
ld.global.u8 %rs1, [%rd8+1];
cvt.s64.s32 %rd9, %r2;
mul.lo.s64 %rd10, %rd9, %rd4;
cvt.s64.s32 %rd11, %r1;
add.s64 %rd12, %rd10, %rd11;
cvta.to.global.u64 %rd13, %rd2;
add.s64 %rd14, %rd13, %rd12;
st.global.u8 [%rd14], %rs1;
BB1_2:
ret;
}
v210_nv12 CUDA_ERROR_MAP_FAILED CUDA_ERROR_ALREADY_MAPPED CUDA_ERROR_ILLEGAL_INSTRUCTION enomem nvenc_select_preset nvenc_init_fail false info fatal pcm_mulaw qp_range fit_w sample_rate gen_pts qsv_err_not_init arg_4_must_be_bin nvenc_encoder_encode_frame: error nvenc_pad %d argb2nv12 init_worker: error thread_create init_graph: ENOMEM init_graph: fail set ch_layout %d %x %s %s input desc for alogo '%s'(%d) ff_load_image: avcodec_open2 failed CUDA_ERROR_PEER_ACCESS_UNSUPPORTED CUDA_ERROR_HOST_MEMORY_ALREADY_REGISTERED second_arg_must_be_binary undefined bitrate background resize_mode deinterlace_rate NvEncodeAPICreateInstance nvenc_process_output nvenc_encoder_alloc: cu_alloc_tex %dx%d %d error %d init_worker: error mutex_create blend_nv12 handle_picture_decode: decoder not found CUDA_ERROR_NOT_READY CUDA_ERROR_PEER_ACCESS_ALREADY_ENABLED CUDA_ERROR_HOST_MEMORY_NOT_REGISTERED debug codec fps in_width qsv_err_aborted nvenc_encode_video: nvenc_trans_init error nvenc_flush_encoder0 nvenc_set_burn0 arg_2_must_bin empty_filter pix_fmts ref init_graph: av_opt_set_int_list %d init_graph: invalid avfilter_get_by_name CUDA_ERROR_ECC_UNCORRECTABLE cuvidReconfigureDecoder nvenc_setup_decoder_worker preset open_gop rc_max_rate filter_spec sample_fmt lib_not_load nvenc_call_bitdepth nvenc_encode_raw: lock error %d H overlay_h ff_load_image_bin: av_find_input_format failed transcoder_streamer_log CUDA_ERROR_UNMAP_FAILED CUDA_ERROR_SHARED_OBJECT_SYMBOL_NOT_FOUND CUDA_ERROR_LAUNCH_FAILED level tff nvenc_init_encode: fps %d/1, DAR %u/%u nvenc_set_logo_bin0 %lu CUDA_ERROR_NOT_INITIALIZED CUDA_ERROR_INVALID_CONTEXT CUDA_ERROR_NOT_PERMITTED veryfast ultrafast nvenc_decode_video: error cuda unmap frame %d nvenc_version0 nvenc_logo_init_bin_fail v210nv12 out nvenc_burn_init: nvenc_burn_get_blank_frame %dx%d 2 ff_load_image: avcodec_send_packet failed sws_getContext fail %dx%d av_hwframe_ctx_init failed %d nvenc_unsupported_device num fit_h qsv_err_inval_handle qsv_err_dev_failed yuv420p10 skip_frame nvenc_trans_init: error %dx%d nvenc_trans_init: unsupported pix_fmt %s(%d) nvenc_burn_init: avfilter_graph_config %x init_graph: avfilter_graph_parse %d video CUDA_ERROR_INVALID_GRAPHICS_CONTEXT CUDA_ERROR_INVALID_SOURCE sar qsv_err_null qsv_err_not_enough unknown cudalock cuvid_unmap nvenc_encode_video: error nvenc_save_prev %d nvenc load: cuDeviceGet error %d nvenc_encode0 nvenc_encode threads logo yadif_cuda=0:-1:0 open_session verbose b bf in_height look_ahead qsv_err_device_lost delta1 nvenc load: cuInit error %s(%d) nvenc load: out of memory av_init_decoder0 nvenc_encoder_alloc crop_tex %dx%d nvenc_encoder_free: nvEncDestroyBitstreamBuffer error %d CUDA_ERROR_NO_BINARY_FOR_GPU CUDA_ERROR_ALREADY_ACQUIRED CUDA_ERROR_OPERATING_SYSTEM CUDA_ERROR_TOO_MANY_PEERS parser_init_fail arg_0_must_be_encoder string uyvy422 win_brc_size qsv_wrn_incompatible_param dlopen nvenc_nomem arg_4_must_be_map nvenc_trans_init: cuMemAllocPitch %dx%d error %d init_graph: avfilter_graph_config %d input desc for logo '%s'(%d) alogo ff_load_image_bin: avio_alloc_context failed CUDA_ERROR_CONTEXT_IS_DESTROYED CUDA_ERROR_HARDWARE_STACK_ERROR reconfigure_fail full simple main10 refs channels vui_video_params arg_2_must_be_pts nvenc_alloc_fail nvenc load: cuDeviceGetName error %d arg_1_must_int drawtext@%s nvenc_encoder_alloc resize_tex %dx%d nvenc_logo: ignore, not load in ff_load_image: av_read_frame failed uint16_to_uint8 argb_nv12 parser_fail bad_map deviceid interlace cu_tex_get_free nvenc_logo_init: parse yexpr fail %s abuffer yadif_deint_send: add_frame failed %d uyvy2nv12 CUDA_ERROR_INVALID_HANDLE warning frame encoder qsv_err_inval_param reconfigure encode_resource beam.vanilla nvenc_decode_video: !cuvidParseVideoData %d trans_init av_hwdevice_ctx_create failed %d CUDA_ERROR_PRIMARY_CONTEXT_ACTIVE mp4_to_annexb keyframe av1 delta2 nvenc_burn_text0 failed_to_open_decoder nvenc_encoder_free: nvEncUnregisterResource error %d nvenc_burn_init: avfilter_graph_parse_ptr %s %x av_read_frame: avcodec_receive_frame failed av_dict_set load_bitdepth_funcs CUDA_ERROR_OUT_OF_MEMORY CUDA_ERROR_ASSERT nvencoder reconfigure_encoder_not_supported true mjpeg qpminp $transcoder_log nvenc load: no CUDA capable device found lock arg_1_must_bin nvenc_trans_upload: error %s %p/%lu %dx%d %p/%lu %dx%d %d init_graph: av_opt_set_bin sample_fmts %d
interleaveChroma init_hw_video_graph fail load_resize CUDA_ERROR_INVALID_PC nvenc_out_of_memory main input_pix_fmt vmemcount filter bff_separated field decode_resource filter_decode_video: get_frame error %d nvenc_decode_video: lock error %d nvenc_init_encode: dar reduced WxH %ux%u yadif_send nvenc_init_encoder0 nvenc_flush_decoder0 nvenc_reconfigure_encoder0 nvenc_pad: ignore, not found nvenc_burn_init: av_opt_set_int_list %x ff_load_image: av_frame_alloc failed blend_rgba_nv12 crop_nv12_nv12 CUDA_ERROR_INVALID_PTX CUDA_ERROR_FILE_NOT_FOUND nvenc_dyload_cuvid: fail load libnvcuvid.so.1 nvenc_setup_encoder_worker fast temporal_tradeoff async dsurfaces qsv_err_lock cuda_copy nvenc_encoder_encode_frame: cuda_alogo fail %d nvenc_encoder_encode_frame: fail map %d nvenc_logo_init: parse xexpr fail %s x init_graph: avfilter_graph_create_filter %d ff_load_image_bin: av_malloc failed ff_load_image_bin: avformat_alloc_context failed %g load_argb_nv12 CUDA_ERROR_NVLINK_UNCORRECTABLE CUDA_ERROR_MISALIGNED_ADDRESS arg_0_must_be_decoder arg_3_must_be_int_pts den extra win_brc_avg dlsym too_big nvenc_load yadif_deint nvenc_init_encode: dar from WxH %ux%u trans_upload save_prev nvenc_encoder_alloc: cuvidCtxLock error %d nvenc_encoder_encode_frame: cuda_logo fail %d init_graph: avfilter_init_dict %d abuffersink ff_load_image: avcodec_alloc_context3 failed blend_rgba_p016 CUDA_ERROR_DEINITIALIZED CUDA_ERROR_NOT_FOUND CUDA_ERROR_PEER_ACCESS_NOT_ENABLED arg_2_must_be_map libx265 left driver_not_load zerocopyframe yadif_deint_send error %d nvenc_get_seq_params: fail nvEncGetSequenceParams %d nvenc_dyload_nvenc: fail load libnvidia-encode.so.1 ff_load_image_bin: bad sar ptr !cuvidCreateVideoParser %d decoder_reconf cuda_ctx_create load_color arg_1_must_be_binary bad_width error panic yuv medium vbv_bufsize fit_y crop vbv_delay lib_not_found no_permission qsv_err_mem cuvid_parser init_graph: av_buffersrc_parameters_set %d ff_load_image: failed no nb_streams ff_load_image: input_desc or time_base is NULL handle_picture_decode: cuda_decoder_decode_picture fail %d Subsample_Bilinear_ushort2 CUDA_ERROR_ILLEGAL_ADDRESS CUDA_ERROR_COOPERATIVE_LAUNCH_TOO_LARGE CUDA_ERROR_UNKNOWN libnvcuvid.so.1 nvenc nvdecoder decoder gop strategy decode_internal nvenc_fps_swap nvenc_init_decoder0_nif arg_3_must_bin W %d CUDA_ERROR_PROFILER_ALREADY_STARTED CUDA_ERROR_INVALID_DEVICE CUDA_ERROR_INVALID_IMAGE cuda_lock baseline width height audio erts-14.0 make_zerocopy_avterm: copy frame to cuda fail %d nvenc_encode0_video: error encode frame %d nvenc burn: cuda_copy: %d nvenc_logo_init: ff_load_image fail %d buffer png_pipe ff_load_image_bin: avformat_open_input failed blend_p016 cu_tex_get_free %d %dx%d %d %d Subsample_Bilinear_ushort load_uyvy2yv12 load_blend_rgba cu_copy_tex: %dx%d:%d != %dx%d:%d arg_2_must_be_int_dts fail load sym cuvidReconfigureDecoder from libnvcuvid.so.1 bad_value quiet qpmini rgb48 rc_buffer_size air zerocopy qsv_err_unsup qsv_err_unknow blur nvenc_decode_video: error cuda map frame %d cuvid_map yadif_alloc cuda_copy_to_frame failed %d !cuvidDestroyDecoder %d Subsample_Bilinear_uchar bad_height encode_destructor: error lock v210 high qpmaxb top input_channel_layout bff nvenc load: cuDeviceGetCount error %s(%d) filter_decode_video: error av_buffersrc_add_frame: %d nvenc_decode0 nvenc_device_list: error %s(%d) nvenc_get_seq_params: nvEncGetSequenceParams %d init_graph: %s input:(%s) filter:(%s), pix_fmt: %d CUDA_ERROR_NOT_MAPPED CUDA_ERROR_NOT_MAPPED_AS_POINTER CUDA_ERROR_LAUNCH_INCOMPATIBLE_TEXTURING need_4_args deinterlace qpmaxp yuyv422 input_sample_fmt nvenc found device id:%d name:%s nvencfps: to many fps frames delta:%ld pts:%ld nvenc_encode_raw: upload error %d nvenc_burn_init_fail reinit nvenc_fps_alloc: cu_tex_alloc error init_graph: av_opt_set_bin channel_layouts %d CUDA_ERROR_PROFILER_NOT_INITIALIZED CUDA_ERROR_NOT_MAPPED_AS_ARRAY dimensions hevc fit fit_x instance nvenc_reconfigure_decoder0 nvenc_dyload_nvenc: fail nvEncodeAPICreateInstance %d nvenc_trans_upload: error cuda_copy %p %lu %p/%lu %dx%d %d %d buffersink nvenc_burn_init: avfilter_graph_create_filter %s %x main_h %s_cond %s_mutex sample_fmts filter spec with logo '%s' av_hwframe_get_buffer failed %d load_v210_nv12 CUDA_ERROR_NO_DEVICE CUDA_ERROR_ARRAY_IS_MAPPED CUDA_ERROR_SHARED_OBJECT_INIT_FAILED CUDA_ERROR_INVALID_ADDRESS_SPACE ok pcm_alaw cuda nvenc_encode0_video: error lock %d nvenc_remove_logo_bin0 text='%s' nvenc_dyload_nvenc: dyload ok nvenc_encoder_alloc: nvenc_fps_alloc fail nvenc_encoder_free: fail nvEncUnmapInputResource %d nvenc_encoder_encode_frame: error cuda_nv12_resize %d nvenc_logo_init: inval image format %d main_w overlay_w y %ld video_size=%dx%d:pix_fmt=%d:time_base=%d/%d:pixel_aspect=%d/%d nvdec handle_video_sequence: !cuvidGetDecoderCaps %d load_crop_func CUDA_ERROR_PROFILER_DISABLED CUDA_ERROR_CONTEXT_ALREADY_CURRENT CUDA_ERROR_LAUNCH_OUT_OF_RESOURCES h264 slow yuv420p rc_min_rate qsv_err_incompatible_param libnvidia-encode.so.1 decode_video: error init_hw_video_graph yadif_recv filter_error nvenc_encoder_alloc: fail nvEncRegisterResource %d nvenc_encoder_alloc: fail cuvidCtxUnlock %d w init_worker: error cond_create init_graph: av_opt_set_bin %d ff_load_image: find stream info failed ff_load_image: frame_get_buffer fail %dx%d uint8_to_uint16 CUDA_ERROR_PROFILER_ALREADY_STOPPED CUDA_ERROR_LAUNCH_TIMEOUT send_packet nvenc_inval_param nvenc_reconfigure_encoder: not supported mp2v libx264 profile bframes subme yadif fit_ratio in_sar input_sample_rate nvenc burn: error av_buffersrc_add_frame_flags: %x init_graph: avfilter_graph_alloc_filter nvdec handle_video_sequence: unsupported codec %d/%d/%d CUDA_ERROR_JIT_COMPILER_NOT_FOUND mp2 align size argb driver_version qsv_err_gpu_hang hw_platform zero_copy_resource arg_3_must_be_bool nvenc_encode_video: nvenc_encoder_alloc error %d nvenc_encoder_encode_frame: cuda_burn fail %d nvenc_burn_init: avfilter_graph_create_filter %x ff_load_image: avcodec_find_decoder failed handle_video_sequence: cuvidCreateDecoder err:%d surfaces:%u deint:%d CUDA_ERROR_INVALID_VALUE CUDA_ERROR_UNSUPPORTED_LIMIT nvenc_no_encode_device unsupported_param bad_option mpeg2video config rc_method qpminb pix_fmt dthreads tff_separated cu_tex_get_free error nvenc_encoder_alloc: nvEncCreateBitstreamBuffer %d nvenc_encoder_encode_frame: error cuda_nv12_crop %d nvenc_burn_init: cuMemAllocPitch %dx%d h ch_layouts init_graph: fail set sample_fmts %x %s ff_load_image_bin: no png image data Subsample_Bilinear_uchar2 CUDA_ERROR_CONTEXT_ALREADY_IN_USE CUDA_ERROR_NOT_SUPPORTED !cuvidParseVideoData %d qpmaxi input_channels channel_layout nvenc2_decode_video: fail filter yadif_deint_recv error %s %d arg_1_must_be_binary_resource nvenc_assert nvenc_device_list0 nvenc_dyload_nvenc: fail load sym NvEncodeAPICreateInstance from libnvidia-encode.so.1 nvenc burn: ignore, not load //
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-21554848
// Cuda compilation tools, release 8.0, V8.0.61
// Based on LLVM 3.4svn
//
.version 5.0
.target sm_20
.address_size 64
// .globl blend_rgba_nv12
.global .align 4 .b8 apix[4] = {16, 128, 128, 0};
.visible .entry blend_rgba_nv12(
.param .u64 blend_rgba_nv12_param_0,
.param .u64 blend_rgba_nv12_param_1,
.param .u32 blend_rgba_nv12_param_2,
.param .u32 blend_rgba_nv12_param_3,
.param .u64 blend_rgba_nv12_param_4,
.param .u64 blend_rgba_nv12_param_5,
.param .u32 blend_rgba_nv12_param_6,
.param .u32 blend_rgba_nv12_param_7,
.param .u32 blend_rgba_nv12_param_8,
.param .u32 blend_rgba_nv12_param_9
)
{
.reg .pred %p<13>;
.reg .b16 %rs<33>;
.reg .b32 %r<190>;
.reg .b64 %rd<49>;
ld.param.u64 %rd14, [blend_rgba_nv12_param_0];
ld.param.u64 %rd15, [blend_rgba_nv12_param_1];
ld.param.u32 %r7, [blend_rgba_nv12_param_2];
ld.param.u32 %r8, [blend_rgba_nv12_param_3];
ld.param.u64 %rd17, [blend_rgba_nv12_param_4];
ld.param.u64 %rd16, [blend_rgba_nv12_param_5];
ld.param.u32 %r11, [blend_rgba_nv12_param_6];
ld.param.u32 %r12, [blend_rgba_nv12_param_7];
ld.param.u32 %r9, [blend_rgba_nv12_param_8];
ld.param.u32 %r10, [blend_rgba_nv12_param_9];
cvta.to.global.u64 %rd1, %rd17;
mov.u32 %r13, %ctaid.x;
mov.u32 %r14, %ntid.x;
mov.u32 %r15, %tid.x;
mad.lo.s32 %r1, %r13, %r14, %r15;
shl.b32 %r2, %r1, 1;
mov.u32 %r16, %ctaid.y;
mov.u32 %r17, %ntid.y;
mov.u32 %r18, %tid.y;
mad.lo.s32 %r19, %r16, %r17, %r18;
shl.b32 %r3, %r19, 1;
setp.gt.u32 %p2, %r2, %r11;
setp.gt.u32 %p3, %r3, %r12;
or.pred %p4, %p2, %p3;
@%p4 bra BB0_6;
add.s32 %r4, %r2, %r9;
setp.gt.u32 %p5, %r4, %r7;
add.s32 %r5, %r3, %r10;
setp.gt.u32 %p6, %r5, %r8;
or.pred %p7, %p5, %p6;
or.b32 %r20, %r5, %r4;
setp.lt.s32 %p8, %r20, 0;
or.pred %p9, %p7, %p8;
@%p9 bra BB0_6;
and.b32 %r21, %r9, 1;
setp.eq.b32 %p1, %r21, 1;
setp.eq.s32 %p10, %r2, 0;
and.pred %p11, %p10, %p1;
cvt.s64.s32 %rd18, %r3;
mul.lo.s64 %rd2, %rd18, %rd16;
add.s32 %r22, %r3, 1;
cvt.s64.s32 %rd19, %r22;
mul.lo.s64 %rd3, %rd19, %rd16;
shl.b32 %r6, %r1, 3;
@%p11 bra BB0_4;
bra.uni BB0_3;
BB0_4:
cvt.s64.s32 %rd25, %r6;
add.s64 %rd46, %rd2, %rd25;
add.s64 %rd48, %rd3, %rd25;
mov.u64 %rd45, apix;
mov.u64 %rd47, %rd45;
bra.uni BB0_5;
BB0_3:
setp.eq.b32 %p12, %r21, 1;
add.s32 %r24, %r2, -1;
shl.b32 %r25, %r24, 2;
selp.b32 %r26, %r25, %r6, %p12;
cvt.s64.s32 %rd20, %r26;
add.s64 %rd21, %rd2, %rd20;
add.s64 %rd22, %rd3, %rd20;
add.s64 %rd47, %rd1, %rd22;
add.s64 %rd45, %rd1, %rd21;
add.s64 %rd48, %rd22, 4;
add.s64 %rd46, %rd21, 4;
BB0_5:
cvta.to.global.u64 %rd26, %rd14;
selp.u32 %r27, 1, 0, %p1;
and.b32 %r28, %r10, 1;
cvt.s64.s32 %rd27, %r5;
mul.lo.s64 %rd28, %rd27, %rd15;
cvt.s64.s32 %rd29, %r4;
add.s64 %rd30, %rd28, %rd29;
add.s64 %rd31, %rd26, %rd30;
add.s64 %rd32, %rd30, %rd15;
add.s64 %rd33, %rd26, %rd32;
ld.global.v4.u8 {%rs1, %rs2, %rs3, %rs4}, [%rd45];
cvt.u32.u16 %r29, %rs4;
add.s32 %r30, %r29, 1;
cvt.u32.u16 %r31, %rs3;
mul.wide.u16 %r32, %rs1, 66;
mul.wide.u16 %r33, %rs2, 129;
add.s32 %r34, %r32, %r33;
add.s32 %r35, %r34, 128;
mad.lo.s32 %r36, %r31, 25, %r35;
shr.u32 %r37, %r36, 8;
add.s32 %r38, %r37, 16;
and.b32 %r39, %r38, 255;
mov.u32 %r40, 256;
sub.s32 %r41, %r40, %r29;
ld.global.u8 %r42, [%rd31];
mul.lo.s32 %r43, %r42, %r41;
mad.lo.s32 %r44, %r39, %r30, %r43;
shr.u32 %r45, %r44, 8;
ld.global.u8 %r46, [%rd31+1];
st.global.u8 [%rd31], %r45;
add.s64 %rd34, %rd1, %rd46;
ld.global.v4.u8 {%rs5, %rs6, %rs7, %rs8}, [%rd34];
cvt.u32.u16 %r47, %rs8;
add.s32 %r48, %r47, 1;
cvt.u32.u16 %r49, %rs7;
mul.wide.u16 %r50, %rs5, 66;
mul.wide.u16 %r51, %rs6, 129;
add.s32 %r52, %r50, %r51;
add.s32 %r53, %r52, 128;
mad.lo.s32 %r54, %r49, 25, %r53;
shr.u32 %r55, %r54, 8;
add.s32 %r56, %r55, 16;
and.b32 %r57, %r56, 255;
sub.s32 %r58, %r40, %r47;
mul.lo.s32 %r59, %r46, %r58;
mad.lo.s32 %r60, %r57, %r48, %r59;
shr.u32 %r61, %r60, 8;
st.global.u8 [%rd31+1], %r61;
ld.global.v4.u8 {%rs9, %rs10, %rs11, %rs12}, [%rd47];
cvt.u32.u16 %r62, %rs12;
add.s32 %r63, %r62, 1;
cvt.u32.u16 %r64, %rs11;
mul.wide.u16 %r65, %rs9, 66;
mul.wide.u16 %r66, %rs10, 129;
add.s32 %r67, %r65, %r66;
add.s32 %r68, %r67, 128;
mad.lo.s32 %r69, %r64, 25, %r68;
shr.u32 %r70, %r69, 8;
add.s32 %r71, %r70, 16;
and.b32 %r72, %r71, 255;
sub.s32 %r73, %r40, %r62;
ld.global.u8 %r74, [%rd33];
mul.lo.s32 %r75, %r74, %r73;
mad.lo.s32 %r76, %r72, %r63, %r75;
shr.u32 %r77, %r76, 8;
ld.global.u8 %r78, [%rd33+1];
st.global.u8 [%rd33], %r77;
add.s64 %rd35, %rd1, %rd48;
ld.global.v4.u8 {%rs13, %rs14, %rs15, %rs16}, [%rd35];
cvt.u32.u16 %r79, %rs16;
add.s32 %r80, %r79, 1;
cvt.u32.u16 %r81, %rs15;
mul.wide.u16 %r82, %rs13, 66;
mul.wide.u16 %r83, %rs14, 129;
add.s32 %r84, %r82, %r83;
add.s32 %r85, %r84, 128;
mad.lo.s32 %r86, %r81, 25, %r85;
shr.u32 %r87, %r86, 8;
add.s32 %r88, %r87, 16;
and.b32 %r89, %r88, 255;
sub.s32 %r90, %r40, %r79;
mul.lo.s32 %r91, %r78, %r90;
mad.lo.s32 %r92, %r89, %r80, %r91;
shr.u32 %r93, %r92, 8;
st.global.u8 [%rd33+1], %r93;
cvt.u64.u32 %rd36, %r8;
mul.lo.s64 %rd37, %rd36, %rd15;
sub.s32 %r94, %r4, %r27;
cvt.u64.u32 %rd38, %r94;
add.s64 %rd39, %rd38, %rd37;
sub.s32 %r95, %r5, %r28;
cvt.u64.u32 %rd40, %r95;
mul.lo.s64 %rd41, %rd40, %rd15;
shr.u64 %rd42, %rd41, 1;
add.s64 %rd43, %rd39, %rd42;
add.s64 %rd44, %rd26, %rd43;
ld.global.v4.u8 {%rs17, %rs18, %rs19, %rs20}, [%rd45];
cvt.u32.u16 %r96, %rs20;
cvt.u32.u16 %r97, %rs19;
cvt.u32.u16 %r98, %rs18;
cvt.u32.u16 %r99, %rs17;
mul.lo.s32 %r100, %r98, -74;
mad.lo.s32 %r101, %r99, -38, %r100;
add.s32 %r102, %r101, 128;
mad.lo.s32 %r103, %r97, 112, %r102;
shr.u32 %r104, %r103, 8;
add.s32 %r105, %r104, 128;
and.b32 %r106, %r105, 255;
ld.global.v4.u8 {%rs21, %rs22, %rs23, %rs24}, [%rd34];
cvt.u32.u16 %r107, %rs24;
cvt.u32.u16 %r108, %rs23;
cvt.u32.u16 %r109, %rs22;
cvt.u32.u16 %r110, %rs21;
mul.lo.s32 %r111, %r109, -74;
mad.lo.s32 %r112, %r110, -38, %r111;
add.s32 %r113, %r112, 128;
mad.lo.s32 %r114, %r108, 112, %r113;
shr.u32 %r115, %r114, 8;
add.s32 %r116, %r115, 128;
and.b32 %r117, %r116, 255;
add.s32 %r118, %r117, %r106;
ld.global.v4.u8 {%rs25, %rs26, %rs27, %rs28}, [%rd47];
cvt.u32.u16 %r119, %rs28;
cvt.u32.u16 %r120, %rs27;
cvt.u32.u16 %r121, %rs26;
cvt.u32.u16 %r122, %rs25;
mul.lo.s32 %r123, %r121, -74;
mad.lo.s32 %r124, %r122, -38, %r123;
add.s32 %r125, %r124, 128;
mad.lo.s32 %r126, %r120, 112, %r125;
shr.u32 %r127, %r126, 8;
add.s32 %r128, %r127, 128;
and.b32 %r129, %r128, 255;
add.s32 %r130, %r118, %r129;
ld.global.v4.u8 {%rs29, %rs30, %rs31, %rs32}, [%rd35];
cvt.u32.u16 %r131, %rs32;
cvt.u32.u16 %r132, %rs31;
cvt.u32.u16 %r133, %rs30;
cvt.u32.u16 %r134, %rs29;
mul.lo.s32 %r135, %r133, -74;
mad.lo.s32 %r136, %r134, -38, %r135;
add.s32 %r137, %r136, 128;
mad.lo.s32 %r138, %r132, 112, %r137;
shr.u32 %r139, %r138, 8;
add.s32 %r140, %r139, 128;
and.b32 %r141, %r140, 255;
add.s32 %r142, %r130, %r141;
mul.wide.u16 %r143, %rs17, 112;
mad.lo.s32 %r144, %r98, -94, %r143;
add.s32 %r145, %r144, 128;
mad.lo.s32 %r146, %r97, -18, %r145;
shr.u32 %r147, %r146, 8;
add.s32 %r148, %r147, 128;
and.b32 %r149, %r148, 255;
mul.wide.u16 %r150, %rs21, 112;
mad.lo.s32 %r151, %r109, -94, %r150;
add.s32 %r152, %r151, 128;
mad.lo.s32 %r153, %r108, -18, %r152;
shr.u32 %r154, %r153, 8;
add.s32 %r155, %r154, 128;
and.b32 %r156, %r155, 255;
add.s32 %r157, %r156, %r149;
mul.wide.u16 %r158, %rs25, 112;
mad.lo.s32 %r159, %r121, -94, %r158;
add.s32 %r160, %r159, 128;
mad.lo.s32 %r161, %r120, -18, %r160;
shr.u32 %r162, %r161, 8;
add.s32 %r163, %r162, 128;
and.b32 %r164, %r163, 255;
add.s32 %r165, %r157, %r164;
mul.wide.u16 %r166, %rs29, 112;
mad.lo.s32 %r167, %r133, -94, %r166;
add.s32 %r168, %r167, 128;
mad.lo.s32 %r169, %r132, -18, %r168;
shr.u32 %r170, %r169, 8;
add.s32 %r171, %r170, 128;
and.b32 %r172, %r171, 255;
add.s32 %r173, %r165, %r172;
add.s32 %r174, %r107, %r96;
add.s32 %r175, %r174, %r119;
add.s32 %r176, %r175, %r131;
bfe.u32 %r177, %r176, 2, 8;
add.s32 %r178, %r177, 1;
bfe.u32 %r179, %r142, 2, 8;
sub.s32 %r180, %r40, %r177;
ld.global.u8 %r181, [%rd44];
mul.lo.s32 %r182, %r180, %r181;
mad.lo.s32 %r183, %r178, %r179, %r182;
shr.u32 %r184, %r183, 8;
ld.global.u8 %r185, [%rd44+1];
st.global.u8 [%rd44], %r184;
bfe.u32 %r186, %r173, 2, 8;
mul.lo.s32 %r187, %r180, %r185;
mad.lo.s32 %r188, %r178, %r186, %r187;
shr.u32 %r189, %r188, 8;
st.global.u8 [%rd44+1], %r189;
BB0_6:
ret;
}
// .globl blend_rgba_p016
.visible .entry blend_rgba_p016(
.param .u64 blend_rgba_p016_param_0,
.param .u64 blend_rgba_p016_param_1,
.param .u32 blend_rgba_p016_param_2,
.param .u32 blend_rgba_p016_param_3,
.param .u64 blend_rgba_p016_param_4,
.param .u64 blend_rgba_p016_param_5,
.param .u32 blend_rgba_p016_param_6,
.param .u32 blend_rgba_p016_param_7,
.param .u32 blend_rgba_p016_param_8,
.param .u32 blend_rgba_p016_param_9
)
{
.reg .pred %p<13>;
.reg .b16 %rs<33>;
.reg .b32 %r<195>;
.reg .b64 %rd<51>;
ld.param.u64 %rd13, [blend_rgba_p016_param_0];
ld.param.u64 %rd14, [blend_rgba_p016_param_1];
ld.param.u32 %r7, [blend_rgba_p016_param_2];
ld.param.u32 %r8, [blend_rgba_p016_param_3];
ld.param.u64 %rd15, [blend_rgba_p016_param_4];
ld.param.u64 %rd16, [blend_rgba_p016_param_5];
ld.param.u32 %r11, [blend_rgba_p016_param_6];
ld.param.u32 %r12, [blend_rgba_p016_param_7];
ld.param.u32 %r9, [blend_rgba_p016_param_8];
ld.param.u32 %r10, [blend_rgba_p016_param_9];
mov.u32 %r13, %ctaid.x;
mov.u32 %r14, %ntid.x;
mov.u32 %r15, %tid.x;
mad.lo.s32 %r1, %r13, %r14, %r15;
shl.b32 %r2, %r1, 1;
mov.u32 %r16, %ctaid.y;
mov.u32 %r17, %ntid.y;
mov.u32 %r18, %tid.y;
mad.lo.s32 %r19, %r16, %r17, %r18;
shl.b32 %r3, %r19, 1;
setp.gt.u32 %p2, %r2, %r11;
setp.gt.u32 %p3, %r3, %r12;
or.pred %p4, %p2, %p3;
@%p4 bra BB1_6;
add.s32 %r4, %r2, %r9;
setp.gt.u32 %p5, %r4, %r7;
add.s32 %r5, %r3, %r10;
setp.gt.u32 %p6, %r5, %r8;
or.pred %p7, %p5, %p6;
or.b32 %r20, %r5, %r4;
setp.lt.s32 %p8, %r20, 0;
or.pred %p9, %p7, %p8;
@%p9 bra BB1_6;
and.b32 %r21, %r9, 1;
setp.eq.b32 %p1, %r21, 1;
setp.eq.s32 %p10, %r2, 0;
and.pred %p11, %p10, %p1;
cvt.s64.s32 %rd17, %r3;
mul.lo.s64 %rd1, %rd17, %rd16;
add.s32 %r22, %r3, 1;
cvt.s64.s32 %rd18, %r22;
mul.lo.s64 %rd2, %rd18, %rd16;
shl.b32 %r6, %r1, 3;
@%p11 bra BB1_4;
bra.uni BB1_3;
BB1_4:
cvt.s64.s32 %rd25, %r6;
add.s64 %rd48, %rd1, %rd25;
add.s64 %rd50, %rd2, %rd25;
mov.u64 %rd47, apix;
mov.u64 %rd49, %rd47;
bra.uni BB1_5;
BB1_3:
cvta.to.global.u64 %rd19, %rd15;
setp.eq.b32 %p12, %r21, 1;
add.s32 %r24, %r2, -1;
shl.b32 %r25, %r24, 2;
selp.b32 %r26, %r25, %r6, %p12;
cvt.s64.s32 %rd20, %r26;
add.s64 %rd21, %rd1, %rd20;
add.s64 %rd22, %rd2, %rd20;
add.s64 %rd49, %rd19, %rd22;
add.s64 %rd47, %rd19, %rd21;
add.s64 %rd50, %rd22, 4;
add.s64 %rd48, %rd21, 4;
BB1_5:
selp.u32 %r27, 1, 0, %p1;
and.b32 %r28, %r10, 1;
shr.u64 %rd26, %rd14, 1;
cvt.u32.u64 %r29, %rd26;
mul.lo.s32 %r30, %r5, %r29;
cvt.u64.u32 %rd27, %r30;
cvt.s64.s32 %rd28, %r4;
add.s64 %rd29, %rd27, %rd28;
cvta.to.global.u64 %rd30, %rd13;
shl.b64 %rd31, %rd29, 1;
add.s64 %rd32, %rd30, %rd31;
and.b64 %rd33, %rd26, 4294967295;
add.s64 %rd34, %rd29, %rd33;
shl.b64 %rd35, %rd34, 1;
add.s64 %rd36, %rd30, %rd35;
ld.global.v4.u8 {%rs1, %rs2, %rs3, %rs4}, [%rd47];
cvt.u32.u16 %r31, %rs4;
add.s32 %r32, %r31, 1;
cvt.u32.u16 %r33, %rs3;
mul.wide.u16 %r34, %rs1, 66;
mul.wide.u16 %r35, %rs2, 129;
add.s32 %r36, %r34, %r35;
add.s32 %r37, %r36, 128;
mad.lo.s32 %r38, %r33, 25, %r37;
shr.u32 %r39, %r38, 8;
add.s32 %r40, %r39, 16;
and.b32 %r41, %r40, 255;
mov.u32 %r42, 256;
sub.s32 %r43, %r42, %r31;
ld.global.u8 %r44, [%rd32+1];
mul.lo.s32 %r45, %r44, %r43;
mad.lo.s32 %r46, %r41, %r32, %r45;
shr.u32 %r47, %r46, 8;
ld.global.u8 %r48, [%rd32+3];
st.global.u8 [%rd32+1], %r47;
cvta.to.global.u64 %rd37, %rd15;
add.s64 %rd38, %rd37, %rd48;
ld.global.v4.u8 {%rs5, %rs6, %rs7, %rs8}, [%rd38];
cvt.u32.u16 %r49, %rs8;
add.s32 %r50, %r49, 1;
cvt.u32.u16 %r51, %rs7;
mul.wide.u16 %r52, %rs5, 66;
mul.wide.u16 %r53, %rs6, 129;
add.s32 %r54, %r52, %r53;
add.s32 %r55, %r54, 128;
mad.lo.s32 %r56, %r51, 25, %r55;
shr.u32 %r57, %r56, 8;
add.s32 %r58, %r57, 16;
and.b32 %r59, %r58, 255;
sub.s32 %r60, %r42, %r49;
mul.lo.s32 %r61, %r48, %r60;
mad.lo.s32 %r62, %r59, %r50, %r61;
shr.u32 %r63, %r62, 8;
st.global.u8 [%rd32+3], %r63;
ld.global.v4.u8 {%rs9, %rs10, %rs11, %rs12}, [%rd49];
cvt.u32.u16 %r64, %rs12;
add.s32 %r65, %r64, 1;
cvt.u32.u16 %r66, %rs11;
mul.wide.u16 %r67, %rs9, 66;
mul.wide.u16 %r68, %rs10, 129;
add.s32 %r69, %r67, %r68;
add.s32 %r70, %r69, 128;
mad.lo.s32 %r71, %r66, 25, %r70;
shr.u32 %r72, %r71, 8;
add.s32 %r73, %r72, 16;
and.b32 %r74, %r73, 255;
sub.s32 %r75, %r42, %r64;
ld.global.u8 %r76, [%rd36+1];
mul.lo.s32 %r77, %r76, %r75;
mad.lo.s32 %r78, %r74, %r65, %r77;
shr.u32 %r79, %r78, 8;
ld.global.u8 %r80, [%rd36+3];
st.global.u8 [%rd36+1], %r79;
add.s64 %rd39, %rd37, %rd50;
ld.global.v4.u8 {%rs13, %rs14, %rs15, %rs16}, [%rd39];
cvt.u32.u16 %r81, %rs16;
add.s32 %r82, %r81, 1;
cvt.u32.u16 %r83, %rs15;
mul.wide.u16 %r84, %rs13, 66;
mul.wide.u16 %r85, %rs14, 129;
add.s32 %r86, %r84, %r85;
add.s32 %r87, %r86, 128;
mad.lo.s32 %r88, %r83, 25, %r87;
shr.u32 %r89, %r88, 8;
add.s32 %r90, %r89, 16;
and.b32 %r91, %r90, 255;
sub.s32 %r92, %r42, %r81;
mul.lo.s32 %r93, %r80, %r92;
mad.lo.s32 %r94, %r91, %r82, %r93;
shr.u32 %r95, %r94, 8;
st.global.u8 [%rd36+3], %r95;
mul.lo.s32 %r96, %r29, %r8;
cvt.u64.u32 %rd40, %r96;
sub.s32 %r97, %r4, %r27;
cvt.u64.u32 %rd41, %r97;
add.s64 %rd42, %rd41, %rd40;
sub.s32 %r98, %r5, %r28;
mul.lo.s32 %r99, %r98, %r29;
shr.u32 %r100, %r99, 1;
cvt.u64.u32 %rd43, %r100;
add.s64 %rd44, %rd42, %rd43;
shl.b64 %rd45, %rd44, 1;
add.s64 %rd46, %rd30, %rd45;
ld.global.v4.u8 {%rs17, %rs18, %rs19, %rs20}, [%rd47];
cvt.u32.u16 %r101, %rs20;
cvt.u32.u16 %r102, %rs19;
cvt.u32.u16 %r103, %rs18;
cvt.u32.u16 %r104, %rs17;
mul.lo.s32 %r105, %r103, -74;
mad.lo.s32 %r106, %r104, -38, %r105;
add.s32 %r107, %r106, 128;
mad.lo.s32 %r108, %r102, 112, %r107;
shr.u32 %r109, %r108, 8;
add.s32 %r110, %r109, 128;
and.b32 %r111, %r110, 255;
ld.global.v4.u8 {%rs21, %rs22, %rs23, %rs24}, [%rd38];
cvt.u32.u16 %r112, %rs24;
cvt.u32.u16 %r113, %rs23;
cvt.u32.u16 %r114, %rs22;
cvt.u32.u16 %r115, %rs21;
mul.lo.s32 %r116, %r114, -74;
mad.lo.s32 %r117, %r115, -38, %r116;
add.s32 %r118, %r117, 128;
mad.lo.s32 %r119, %r113, 112, %r118;
shr.u32 %r120, %r119, 8;
add.s32 %r121, %r120, 128;
and.b32 %r122, %r121, 255;
add.s32 %r123, %r122, %r111;
ld.global.v4.u8 {%rs25, %rs26, %rs27, %rs28}, [%rd49];
cvt.u32.u16 %r124, %rs28;
cvt.u32.u16 %r125, %rs27;
cvt.u32.u16 %r126, %rs26;
cvt.u32.u16 %r127, %rs25;
mul.lo.s32 %r128, %r126, -74;
mad.lo.s32 %r129, %r127, -38, %r128;
add.s32 %r130, %r129, 128;
mad.lo.s32 %r131, %r125, 112, %r130;
shr.u32 %r132, %r131, 8;
add.s32 %r133, %r132, 128;
and.b32 %r134, %r133, 255;
add.s32 %r135, %r123, %r134;
ld.global.v4.u8 {%rs29, %rs30, %rs31, %rs32}, [%rd39];
cvt.u32.u16 %r136, %rs32;
cvt.u32.u16 %r137, %rs31;
cvt.u32.u16 %r138, %rs30;
cvt.u32.u16 %r139, %rs29;
mul.lo.s32 %r140, %r138, -74;
mad.lo.s32 %r141, %r139, -38, %r140;
add.s32 %r142, %r141, 128;
mad.lo.s32 %r143, %r137, 112, %r142;
shr.u32 %r144, %r143, 8;
add.s32 %r145, %r144, 128;
and.b32 %r146, %r145, 255;
add.s32 %r147, %r135, %r146;
mul.wide.u16 %r148, %rs17, 112;
mad.lo.s32 %r149, %r103, -94, %r148;
add.s32 %r150, %r149, 128;
mad.lo.s32 %r151, %r102, -18, %r150;
shr.u32 %r152, %r151, 8;
add.s32 %r153, %r152, 128;
and.b32 %r154, %r153, 255;
mul.wide.u16 %r155, %rs21, 112;
mad.lo.s32 %r156, %r114, -94, %r155;
add.s32 %r157, %r156, 128;
mad.lo.s32 %r158, %r113, -18, %r157;
shr.u32 %r159, %r158, 8;
add.s32 %r160, %r159, 128;
and.b32 %r161, %r160, 255;
add.s32 %r162, %r161, %r154;
mul.wide.u16 %r163, %rs25, 112;
mad.lo.s32 %r164, %r126, -94, %r163;
add.s32 %r165, %r164, 128;
mad.lo.s32 %r166, %r125, -18, %r165;
shr.u32 %r167, %r166, 8;
add.s32 %r168, %r167, 128;
and.b32 %r169, %r168, 255;
add.s32 %r170, %r162, %r169;
mul.wide.u16 %r171, %rs29, 112;
mad.lo.s32 %r172, %r138, -94, %r171;
add.s32 %r173, %r172, 128;
mad.lo.s32 %r174, %r137, -18, %r173;
shr.u32 %r175, %r174, 8;
add.s32 %r176, %r175, 128;
and.b32 %r177, %r176, 255;
add.s32 %r178, %r170, %r177;
add.s32 %r179, %r112, %r101;
add.s32 %r180, %r179, %r124;
add.s32 %r181, %r180, %r136;
bfe.u32 %r182, %r181, 2, 8;
add.s32 %r183, %r182, 1;
bfe.u32 %r184, %r147, 2, 8;
sub.s32 %r185, %r42, %r182;
ld.global.u8 %r186, [%rd46+1];
mul.lo.s32 %r187, %r185, %r186;
mad.lo.s32 %r188, %r183, %r184, %r187;
shr.u32 %r189, %r188, 8;
ld.global.u8 %r190, [%rd46+3];
st.global.u8 [%rd46+1], %r189;
bfe.u32 %r191, %r178, 2, 8;
mul.lo.s32 %r192, %r185, %r190;
mad.lo.s32 %r193, %r183, %r191, %r192;
shr.u32 %r194, %r193, 8;
st.global.u8 [%rd46+3], %r194;
BB1_6:
ret;
}
// .globl blend_nv12
.visible .entry blend_nv12(
.param .u64 blend_nv12_param_0,
.param .u64 blend_nv12_param_1,
.param .u32 blend_nv12_param_2,
.param .u32 blend_nv12_param_3,
.param .u64 blend_nv12_param_4,
.param .u64 blend_nv12_param_5,
.param .u32 blend_nv12_param_6,
.param .u32 blend_nv12_param_7,
.param .u32 blend_nv12_param_8,
.param .u32 blend_nv12_param_9
)
{
.reg .pred %p<17>;
.reg .b16 %rs<16>;
.reg .b32 %r<49>;
.reg .b64 %rd<79>;
ld.param.u64 %rd24, [blend_nv12_param_0];
ld.param.u64 %rd25, [blend_nv12_param_1];
ld.param.u32 %r9, [blend_nv12_param_2];
ld.param.u32 %r10, [blend_nv12_param_3];
ld.param.u64 %rd26, [blend_nv12_param_4];
ld.param.u64 %rd27, [blend_nv12_param_5];
ld.param.u32 %r11, [blend_nv12_param_6];
ld.param.u32 %r12, [blend_nv12_param_7];
ld.param.u32 %r13, [blend_nv12_param_8];
ld.param.u32 %r14, [blend_nv12_param_9];
mov.u32 %r15, %ctaid.x;
mov.u32 %r16, %ntid.x;
mov.u32 %r17, %tid.x;
mad.lo.s32 %r18, %r15, %r16, %r17;
shl.b32 %r1, %r18, 1;
mov.u32 %r19, %ctaid.y;
mov.u32 %r20, %ntid.y;
mov.u32 %r21, %tid.y;
mad.lo.s32 %r22, %r19, %r20, %r21;
shl.b32 %r2, %r22, 1;
setp.ge.u32 %p1, %r2, %r12;
setp.ge.u32 %p2, %r1, %r11;
or.pred %p3, %p1, %p2;
@%p3 bra BB2_16;
add.s32 %r3, %r1, %r13;
add.s32 %r4, %r2, %r14;
setp.ge.u32 %p4, %r4, %r10;
setp.ge.u32 %p5, %r3, %r9;
or.pred %p6, %p4, %p5;
or.b32 %r23, %r4, %r3;
setp.lt.s32 %p7, %r23, 0;
or.pred %p8, %p6, %p7;
@%p8 bra BB2_16;
cvta.to.global.u64 %rd28, %rd24;
and.b32 %r5, %r13, 1;
setp.eq.b32 %p9, %r5, 1;
and.b32 %r24, %r14, 1;
cvt.u32.u64 %r6, %rd27;
cvt.u32.u64 %r25, %rd25;
mul.lo.s32 %r26, %r4, %r25;
cvt.u64.u32 %rd29, %r26;
cvt.s64.s32 %rd30, %r3;
add.s64 %rd31, %rd29, %rd30;
add.s64 %rd1, %rd28, %rd31;
and.b64 %rd32, %rd25, 4294967295;
add.s64 %rd2, %rd31, %rd32;
add.s64 %rd3, %rd28, %rd2;
mul.lo.s32 %r27, %r25, %r10;
cvt.u64.u32 %rd33, %r27;
sub.s32 %r28, %r3, %r5;
cvt.u64.u32 %rd34, %r28;
add.s64 %rd35, %rd34, %rd33;
sub.s32 %r29, %r4, %r24;
mul.lo.s32 %r30, %r29, %r25;
shr.u32 %r31, %r30, 1;
cvt.u64.u32 %rd36, %r31;
add.s64 %rd37, %rd35, %rd36;
add.s64 %rd4, %rd28, %rd37;
setp.eq.s32 %p10, %r1, 0;
and.pred %p11, %p10, %p9;
mul.lo.s32 %r7, %r2, %r6;
cvt.u64.u32 %rd5, %r7;
add.s32 %r8, %r2, 1;
@%p11 bra BB2_14;
bra.uni BB2_3;
BB2_14:
cvta.to.global.u64 %rd65, %rd26;
ld.global.u8 %rs14, [%rd1];
add.s64 %rd66, %rd65, %rd5;
ld.global.u8 %rs15, [%rd66];
mul.lo.s32 %r48, %r8, %r6;
cvt.u64.u32 %rd67, %r48;
add.s64 %rd74, %rd65, %rd67;
mov.u64 %rd72, %rd3;
mov.u64 %rd77, %rd4;
mov.u64 %rd78, %rd77;
bra.uni BB2_15;
BB2_3:
setp.ne.s32 %p12, %r5, 0;
cvt.s64.s32 %rd6, %r1;
add.s64 %rd38, %rd5, %rd6;
cvta.to.global.u64 %rd39, %rd26;
add.s64 %rd7, %rd39, %rd38;
@%p12 bra BB2_11;
bra.uni BB2_4;
BB2_11:
add.s32 %r40, %r1, -1;
cvt.s64.s32 %rd15, %r40;
add.s64 %rd53, %rd5, %rd15;
add.s64 %rd55, %rd39, %rd53;
ld.global.u8 %rs14, [%rd55];
ld.global.u8 %rs15, [%rd7];
setp.lt.u32 %p16, %r8, %r6;
@%p16 bra BB2_13;
bra.uni BB2_12;
BB2_13:
cvt.u32.u64 %r42, %rd5;
mul.lo.s32 %r44, %r8, %r6;
cvt.u64.u32 %rd58, %r44;
add.s64 %rd59, %rd58, %rd15;
add.s64 %rd72, %rd39, %rd59;
add.s64 %rd61, %rd58, %rd6;
add.s64 %rd74, %rd39, %rd61;
shr.u32 %r45, %r42, 1;
add.s32 %r46, %r45, %r1;
cvt.u64.u32 %rd62, %r46;
mul.lo.s32 %r47, %r6, %r12;
cvt.u64.u32 %rd63, %r47;
add.s64 %rd64, %rd62, %rd63;
add.s64 %rd19, %rd39, %rd64;
mov.u64 %rd78, %rd19;
bra.uni BB2_15;
BB2_4:
add.s32 %r32, %r1, 1;
setp.lt.u32 %p13, %r32, %r11;
ld.global.u8 %rs14, [%rd7];
@%p13 bra BB2_8;
bra.uni BB2_5;
BB2_8:
setp.lt.u32 %p15, %r8, %r12;
ld.global.u8 %rs15, [%rd7+1];
@%p15 bra BB2_10;
bra.uni BB2_9;
BB2_10:
mul.lo.s32 %r36, %r8, %r6;
cvt.u64.u32 %rd47, %r36;
add.s64 %rd48, %rd47, %rd6;
add.s64 %rd72, %rd48, %rd39;
add.s64 %rd74, %rd72, 1;
shr.u32 %r37, %r7, 1;
add.s32 %r38, %r37, %r1;
cvt.u64.u32 %rd50, %r38;
mul.lo.s32 %r39, %r6, %r12;
cvt.u64.u32 %rd51, %r39;
add.s64 %rd52, %rd50, %rd51;
add.s64 %rd14, %rd39, %rd52;
mov.u64 %rd78, %rd14;
bra.uni BB2_15;
BB2_12:
add.s64 %rd57, %rd2, %rd28;
add.s64 %rd74, %rd57, 1;
mov.u64 %rd72, %rd3;
mov.u64 %rd76, %rd4;
mov.u64 %rd78, %rd76;
bra.uni BB2_15;
BB2_5:
ld.global.u8 %rs15, [%rd1+1];
setp.ge.u32 %p14, %r8, %r12;
mov.u64 %rd73, %rd3;
@%p14 bra BB2_7;
mul.lo.s32 %r34, %r8, %r6;
cvt.u64.u32 %rd40, %r34;
add.s64 %rd41, %rd40, %rd6;
add.s64 %rd8, %rd39, %rd41;
mov.u64 %rd73, %rd8;
BB2_7:
mov.u64 %rd71, %rd73;
mov.u64 %rd72, %rd71;
add.s64 %rd44, %rd2, %rd28;
add.s64 %rd74, %rd44, 1;
mov.u64 %rd78, %rd4;
bra.uni BB2_15;
BB2_9:
add.s64 %rd46, %rd2, %rd28;
add.s64 %rd74, %rd46, 1;
mov.u64 %rd72, %rd3;
mov.u64 %rd75, %rd4;
mov.u64 %rd78, %rd75;
BB2_15:
mov.u64 %rd23, %rd78;
ld.global.u8 %rs10, [%rd74];
ld.global.u8 %rs11, [%rd72];
st.global.u8 [%rd1], %rs14;
st.global.u8 [%rd1+1], %rs15;
st.global.u8 [%rd3], %rs11;
st.global.u8 [%rd3+1], %rs10;
ld.global.u8 %rs12, [%rd23];
st.global.u8 [%rd4], %rs12;
ld.global.u8 %rs13, [%rd23+1];
st.global.u8 [%rd4+1], %rs13;
BB2_16:
ret;
}
// .globl blend_p016
.visible .entry blend_p016(
.param .u64 blend_p016_param_0,
.param .u64 blend_p016_param_1,
.param .u32 blend_p016_param_2,
.param .u32 blend_p016_param_3,
.param .u64 blend_p016_param_4,
.param .u64 blend_p016_param_5,
.param .u32 blend_p016_param_6,
.param .u32 blend_p016_param_7,
.param .u32 blend_p016_param_8,
.param .u32 blend_p016_param_9
)
{
.reg .pred %p<17>;
.reg .b16 %rs<16>;
.reg .b32 %r<49>;
.reg .b64 %rd<100>;
ld.param.u64 %rd24, [blend_p016_param_0];
ld.param.u64 %rd25, [blend_p016_param_1];
ld.param.u32 %r9, [blend_p016_param_2];
ld.param.u32 %r10, [blend_p016_param_3];
ld.param.u64 %rd26, [blend_p016_param_4];
ld.param.u64 %rd27, [blend_p016_param_5];
ld.param.u32 %r11, [blend_p016_param_6];
ld.param.u32 %r12, [blend_p016_param_7];
ld.param.u32 %r13, [blend_p016_param_8];
ld.param.u32 %r14, [blend_p016_param_9];
mov.u32 %r15, %ctaid.x;
mov.u32 %r16, %ntid.x;
mov.u32 %r17, %tid.x;
mad.lo.s32 %r18, %r15, %r16, %r17;
shl.b32 %r1, %r18, 1;
mov.u32 %r19, %ctaid.y;
mov.u32 %r20, %ntid.y;
mov.u32 %r21, %tid.y;
mad.lo.s32 %r22, %r19, %r20, %r21;
shl.b32 %r2, %r22, 1;
setp.ge.u32 %p1, %r2, %r12;
setp.ge.u32 %p2, %r1, %r11;
or.pred %p3, %p1, %p2;
@%p3 bra BB3_16;
add.s32 %r3, %r1, %r13;
add.s32 %r4, %r2, %r14;
setp.ge.u32 %p4, %r4, %r10;
setp.ge.u32 %p5, %r3, %r9;
or.pred %p6, %p4, %p5;
or.b32 %r23, %r4, %r3;
setp.lt.s32 %p7, %r23, 0;
or.pred %p8, %p6, %p7;
@%p8 bra BB3_16;
cvta.to.global.u64 %rd28, %rd24;
and.b32 %r5, %r13, 1;
setp.eq.b32 %p9, %r5, 1;
and.b32 %r24, %r14, 1;
shr.u64 %rd29, %rd25, 1;
cvt.u32.u64 %r25, %rd29;
shr.u64 %rd30, %rd27, 1;
cvt.u32.u64 %r6, %rd30;
mul.lo.s32 %r26, %r4, %r25;
cvt.u64.u32 %rd31, %r26;
cvt.s64.s32 %rd32, %r3;
add.s64 %rd33, %rd31, %rd32;
shl.b64 %rd34, %rd33, 1;
add.s64 %rd1, %rd28, %rd34;
and.b64 %rd35, %rd29, 4294967295;
add.s64 %rd2, %rd33, %rd35;
shl.b64 %rd36, %rd2, 1;
add.s64 %rd3, %rd28, %rd36;
mul.lo.s32 %r27, %r25, %r10;
cvt.u64.u32 %rd37, %r27;
sub.s32 %r28, %r3, %r5;
cvt.u64.u32 %rd38, %r28;
add.s64 %rd39, %rd38, %rd37;
sub.s32 %r29, %r4, %r24;
mul.lo.s32 %r30, %r29, %r25;
shr.u32 %r31, %r30, 1;
cvt.u64.u32 %rd40, %r31;
add.s64 %rd41, %rd39, %rd40;
shl.b64 %rd42, %rd41, 1;
add.s64 %rd4, %rd28, %rd42;
setp.eq.s32 %p10, %r1, 0;
and.pred %p11, %p10, %p9;
mul.lo.s32 %r7, %r2, %r6;
cvt.u64.u32 %rd5, %r7;
add.s32 %r8, %r2, 1;
@%p11 bra BB3_14;
bra.uni BB3_3;
BB3_14:
cvta.to.global.u64 %rd85, %rd26;
ld.global.u16 %rs14, [%rd1];
shl.b64 %rd86, %rd5, 1;
add.s64 %rd87, %rd85, %rd86;
ld.global.u16 %rs15, [%rd87];
mul.lo.s32 %r48, %r8, %r6;
mul.wide.u32 %rd88, %r48, 2;
add.s64 %rd95, %rd85, %rd88;
mov.u64 %rd93, %rd3;
mov.u64 %rd98, %rd4;
mov.u64 %rd99, %rd98;
bra.uni BB3_15;
BB3_3:
setp.ne.s32 %p12, %r5, 0;
cvt.s64.s32 %rd6, %r1;
add.s64 %rd43, %rd5, %rd6;
cvta.to.global.u64 %rd44, %rd26;
shl.b64 %rd45, %rd43, 1;
add.s64 %rd7, %rd44, %rd45;
@%p12 bra BB3_11;
bra.uni BB3_4;
BB3_11:
add.s32 %r40, %r1, -1;
cvt.s64.s32 %rd15, %r40;
add.s64 %rd66, %rd5, %rd15;
shl.b64 %rd68, %rd66, 1;
add.s64 %rd69, %rd44, %rd68;
ld.global.u16 %rs14, [%rd69];
ld.global.u16 %rs15, [%rd7];
setp.lt.u32 %p16, %r8, %r6;
@%p16 bra BB3_13;
bra.uni BB3_12;
BB3_13:
cvt.u32.u64 %r42, %rd5;
mul.lo.s32 %r44, %r8, %r6;
cvt.u64.u32 %rd75, %r44;
add.s64 %rd76, %rd75, %rd15;
shl.b64 %rd78, %rd76, 1;
add.s64 %rd93, %rd44, %rd78;
add.s64 %rd79, %rd75, %rd6;
shl.b64 %rd80, %rd79, 1;
add.s64 %rd95, %rd44, %rd80;
shr.u32 %r45, %r42, 1;
add.s32 %r46, %r45, %r1;
cvt.u64.u32 %rd81, %r46;
mul.lo.s32 %r47, %r6, %r12;
cvt.u64.u32 %rd82, %r47;
add.s64 %rd83, %rd81, %rd82;
shl.b64 %rd84, %rd83, 1;
add.s64 %rd19, %rd44, %rd84;
mov.u64 %rd99, %rd19;
bra.uni BB3_15;
BB3_4:
add.s32 %r32, %r1, 1;
setp.lt.u32 %p13, %r32, %r11;
ld.global.u16 %rs14, [%rd7];
@%p13 bra BB3_8;
bra.uni BB3_5;
BB3_8:
setp.lt.u32 %p15, %r8, %r12;
ld.global.u16 %rs15, [%rd7+2];
@%p15 bra BB3_10;
bra.uni BB3_9;
BB3_10:
mul.lo.s32 %r36, %r8, %r6;
cvt.u64.u32 %rd58, %r36;
add.s64 %rd60, %rd58, %rd6;
shl.b64 %rd61, %rd60, 1;
add.s64 %rd93, %rd61, %rd44;
add.s64 %rd95, %rd93, 2;
shr.u32 %r37, %r7, 1;
add.s32 %r38, %r37, %r1;
cvt.u64.u32 %rd62, %r38;
mul.lo.s32 %r39, %r6, %r12;
cvt.u64.u32 %rd63, %r39;
add.s64 %rd64, %rd62, %rd63;
shl.b64 %rd65, %rd64, 1;
add.s64 %rd14, %rd44, %rd65;
mov.u64 %rd99, %rd14;
bra.uni BB3_15;
BB3_12:
add.s64 %rd73, %rd36, %rd28;
add.s64 %rd95, %rd73, 2;
mov.u64 %rd93, %rd3;
mov.u64 %rd97, %rd4;
mov.u64 %rd99, %rd97;
bra.uni BB3_15;
BB3_5:
ld.global.u16 %rs15, [%rd1+2];
setp.ge.u32 %p14, %r8, %r12;
mov.u64 %rd94, %rd3;
@%p14 bra BB3_7;
mul.lo.s32 %r34, %r8, %r6;
cvt.u64.u32 %rd47, %r34;
add.s64 %rd48, %rd47, %rd6;
shl.b64 %rd50, %rd48, 1;
add.s64 %rd8, %rd44, %rd50;
mov.u64 %rd94, %rd8;
BB3_7:
mov.u64 %rd92, %rd94;
mov.u64 %rd93, %rd92;
add.s64 %rd53, %rd36, %rd28;
add.s64 %rd95, %rd53, 2;
mov.u64 %rd99, %rd4;
bra.uni BB3_15;
BB3_9:
add.s64 %rd56, %rd36, %rd28;
add.s64 %rd95, %rd56, 2;
mov.u64 %rd93, %rd3;
mov.u64 %rd96, %rd4;
mov.u64 %rd99, %rd96;
BB3_15:
mov.u64 %rd23, %rd99;
ld.global.u16 %rs10, [%rd95];
ld.global.u16 %rs11, [%rd93];
st.global.u16 [%rd1], %rs14;
st.global.u16 [%rd1+2], %rs15;
st.global.u16 [%rd3], %rs11;
st.global.u16 [%rd3+2], %rs10;
ld.global.u16 %rs12, [%rd23];
st.global.u16 [%rd4], %rs12;
ld.global.u16 %rs13, [%rd23+2];
st.global.u16 [%rd4+2], %rs13;
BB3_16:
ret;
}
//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-19830389
// Cuda compilation tools, release 8.0, V8.0.0
// Based on LLVM 3.4svn
//
.version 4.3
.target sm_30
.address_size 64
// .globl interleaveChroma
.visible .entry interleaveChroma(
.param .u64 interleaveChroma_param_0,
.param .u64 interleaveChroma_param_1,
.param .u64 interleaveChroma_param_2,
.param .u32 interleaveChroma_param_3,
.param .u32 interleaveChroma_param_4,
.param .u32 interleaveChroma_param_5,
.param .u32 interleaveChroma_param_6
)
{
.reg .pred %p<5>;
.reg .b32 %r<47>;
.reg .b64 %rd<14>;
ld.param.u64 %rd4, [interleaveChroma_param_0];
ld.param.u64 %rd5, [interleaveChroma_param_1];
ld.param.u64 %rd6, [interleaveChroma_param_2];
ld.param.u32 %r12, [interleaveChroma_param_3];
ld.param.u32 %r15, [interleaveChroma_param_4];
ld.param.u32 %r13, [interleaveChroma_param_5];
ld.param.u32 %r14, [interleaveChroma_param_6];
shr.s32 %r1, %r15, 1;
mov.u32 %r45, %ctaid.x;
setp.ge.s32 %p1, %r45, %r1;
@%p1 bra BB0_6;
cvta.to.global.u64 %rd1, %rd6;
cvta.to.global.u64 %rd2, %rd5;
cvta.to.global.u64 %rd3, %rd4;
mov.u32 %r3, %tid.x;
shr.s32 %r4, %r12, 3;
mov.u32 %r5, %ntid.x;
BB0_2:
setp.ge.s32 %p2, %r3, %r4;
@%p2 bra BB0_5;
mul.lo.s32 %r16, %r45, %r13;
mul.lo.s32 %r17, %r45, %r14;
shr.s32 %r7, %r17, 2;
shr.s32 %r18, %r16, 2;
shr.u32 %r8, %r18, 1;
mov.u32 %r46, %r3;
BB0_4:
mov.u32 %r9, %r46;
add.s32 %r19, %r9, %r8;
mul.wide.u32 %rd7, %r19, 4;
add.s64 %rd8, %rd3, %rd7;
add.s64 %rd9, %rd2, %rd7;
ld.global.u32 %r20, [%rd9];
and.b32 %r21, %r20, 65280;
shl.b32 %r22, %r21, 16;
ld.global.u32 %r23, [%rd8];
shl.b32 %r24, %r23, 8;
and.b32 %r25, %r24, 16711680;
shl.b32 %r26, %r20, 8;
and.b32 %r27, %r26, 65280;
and.b32 %r28, %r23, 255;
or.b32 %r29, %r25, %r28;
or.b32 %r30, %r29, %r22;
or.b32 %r31, %r30, %r27;
shl.b32 %r32, %r9, 1;
add.s32 %r33, %r32, %r7;
mul.wide.u32 %rd10, %r33, 4;
add.s64 %rd11, %rd1, %rd10;
st.global.u32 [%rd11], %r31;
and.b32 %r34, %r20, -16777216;
and.b32 %r35, %r23, -16777216;
shr.u32 %r36, %r35, 8;
or.b32 %r37, %r34, %r36;
and.b32 %r38, %r20, 16711680;
shr.u32 %r39, %r38, 8;
bfe.u32 %r40, %r23, 16, 8;
or.b32 %r41, %r37, %r40;
or.b32 %r42, %r41, %r39;
add.s32 %r43, %r33, 1;
mul.wide.u32 %rd12, %r43, 4;
add.s64 %rd13, %rd1, %rd12;
st.global.u32 [%rd13], %r42;
add.s32 %r10, %r5, %r9;
setp.lt.s32 %p3, %r10, %r4;
mov.u32 %r46, %r10;
@%p3 bra BB0_4;
BB0_5:
mov.u32 %r44, %nctaid.x;
add.s32 %r45, %r44, %r45;
setp.lt.s32 %p4, %r45, %r1;
@%p4 bra BB0_2;
BB0_6:
ret;
}
//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-21124049
// Cuda compilation tools, release 8.0, V8.0.44
// Based on LLVM 3.4svn
//
.version 5.0
.target sm_20
.address_size 64
// .globl crop_nv12_nv12
.visible .entry crop_nv12_nv12(
.param .u64 crop_nv12_nv12_param_0,
.param .u64 crop_nv12_nv12_param_1,
.param .u64 crop_nv12_nv12_param_2,
.param .u64 crop_nv12_nv12_param_3,
.param .u64 crop_nv12_nv12_param_4,
.param .u64 crop_nv12_nv12_param_5,
.param .u64 crop_nv12_nv12_param_6,
.param .u64 crop_nv12_nv12_param_7,
.param .u64 crop_nv12_nv12_param_8
)
{
.reg .pred %p<5>;
.reg .b16 %rs<3>;
.reg .b32 %r<9>;
.reg .b64 %rd<36>;
ld.param.u64 %rd12, [crop_nv12_nv12_param_0];
ld.param.u64 %rd6, [crop_nv12_nv12_param_1];
ld.param.u64 %rd13, [crop_nv12_nv12_param_2];
ld.param.u64 %rd7, [crop_nv12_nv12_param_3];
ld.param.u64 %rd14, [crop_nv12_nv12_param_4];
ld.param.u64 %rd8, [crop_nv12_nv12_param_5];
ld.param.u64 %rd9, [crop_nv12_nv12_param_6];
ld.param.u64 %rd10, [crop_nv12_nv12_param_7];
ld.param.u64 %rd11, [crop_nv12_nv12_param_8];
cvta.to.global.u64 %rd1, %rd12;
cvta.to.global.u64 %rd2, %rd14;
mov.u32 %r2, %ntid.x;
mov.u32 %r3, %ctaid.x;
mov.u32 %r4, %tid.x;
mad.lo.s32 %r1, %r2, %r3, %r4;
mov.u32 %r5, %ntid.y;
mov.u32 %r6, %ctaid.y;
mov.u32 %r7, %tid.y;
mad.lo.s32 %r8, %r5, %r6, %r7;
cvt.s64.s32 %rd15, %r1;
setp.lt.u64 %p1, %rd15, %rd13;
cvt.s64.s32 %rd3, %r8;
setp.lt.u64 %p2, %rd3, %rd7;
and.pred %p3, %p1, %p2;
@!%p3 bra BB0_3;
bra.uni BB0_1;
BB0_1:
mul.lo.s64 %rd16, %rd3, %rd6;
cvt.u64.u32 %rd17, %r1;
add.s64 %rd4, %rd16, %rd17;
add.s64 %rd18, %rd3, %rd11;
mul.lo.s64 %rd19, %rd18, %rd8;
add.s64 %rd20, %rd17, %rd10;
add.s64 %rd5, %rd20, %rd19;
cvt.s64.s32 %rd21, %rd5;
add.s64 %rd22, %rd2, %rd21;
ld.global.u8 %rs1, [%rd22];
cvt.s64.s32 %rd23, %rd4;
add.s64 %rd24, %rd1, %rd23;
st.global.u8 [%rd24], %rs1;
shr.u64 %rd25, %rd7, 1;
setp.ge.u64 %p4, %rd3, %rd25;
@%p4 bra BB0_3;
mul.lo.s64 %rd26, %rd7, %rd6;
add.s64 %rd27, %rd4, %rd26;
shr.u64 %rd28, %rd11, 1;
sub.s64 %rd29, %rd9, %rd28;
mul.lo.s64 %rd30, %rd29, %rd8;
add.s64 %rd31, %rd5, %rd30;
cvt.s64.s32 %rd32, %rd31;
add.s64 %rd33, %rd2, %rd32;
ld.global.u8 %rs2, [%rd33];
cvt.s64.s32 %rd34, %rd27;
add.s64 %rd35, %rd1, %rd34;
st.global.u8 [%rd35], %rs2;
BB0_3:
ret;
}
_ //
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-21554848
// Cuda compilation tools, release 8.0, V8.0.61
// Based on LLVM 3.4svn
//
.version 5.0
.target sm_20
.address_size 64
// .globl Subsample_Bilinear_uchar
.visible .entry Subsample_Bilinear_uchar(
.param .u64 Subsample_Bilinear_uchar_param_0,
.param .u64 Subsample_Bilinear_uchar_param_1,
.param .u32 Subsample_Bilinear_uchar_param_2,
.param .u32 Subsample_Bilinear_uchar_param_3,
.param .u32 Subsample_Bilinear_uchar_param_4,
.param .u32 Subsample_Bilinear_uchar_param_5,
.param .u32 Subsample_Bilinear_uchar_param_6
)
{
.reg .pred %p<4>;
.reg .f32 %f<27>;
.reg .b32 %r<40>;
.reg .b64 %rd<6>;
ld.param.u64 %rd1, [Subsample_Bilinear_uchar_param_0];
ld.param.u64 %rd2, [Subsample_Bilinear_uchar_param_1];
ld.param.u32 %r3, [Subsample_Bilinear_uchar_param_2];
ld.param.u32 %r4, [Subsample_Bilinear_uchar_param_3];
ld.param.u32 %r5, [Subsample_Bilinear_uchar_param_4];
ld.param.u32 %r6, [Subsample_Bilinear_uchar_param_5];
ld.param.u32 %r7, [Subsample_Bilinear_uchar_param_6];
mov.u32 %r8, %ctaid.x;
mov.u32 %r9, %ntid.x;
mov.u32 %r10, %tid.x;
mad.lo.s32 %r1, %r9, %r8, %r10;
mov.u32 %r11, %ntid.y;
mov.u32 %r12, %ctaid.y;
mov.u32 %r13, %tid.y;
mad.lo.s32 %r2, %r11, %r12, %r13;
setp.lt.s32 %p1, %r2, %r4;
setp.lt.s32 %p2, %r1, %r3;
and.pred %p3, %p1, %p2;
@!%p3 bra BB0_2;
bra.uni BB0_1;
BB0_1:
cvt.rn.f32.s32 %f1, %r6;
cvt.rn.f32.s32 %f2, %r3;
div.rn.f32 %f3, %f1, %f2;
cvt.rn.f32.s32 %f4, %r4;
cvt.rn.f32.s32 %f5, %r7;
div.rn.f32 %f6, %f5, %f4;
cvt.rn.f32.s32 %f7, %r1;
add.f32 %f8, %f7, 0f3F000000;
mul.f32 %f9, %f8, %f3;
cvt.rn.f32.s32 %f10, %r2;
add.f32 %f11, %f10, 0f3F000000;
mul.f32 %f12, %f11, %f6;
add.f32 %f13, %f3, 0fBF800000;
mul.f32 %f14, %f13, 0f3F000000;
cvt.sat.f32.f32 %f15, %f14;
add.f32 %f16, %f6, 0fBF800000;
mul.f32 %f17, %f16, 0f3F000000;
cvt.sat.f32.f32 %f18, %f17;
add.f32 %f19, %f15, 0f3F000000;
div.rn.f32 %f20, %f15, %f19;
add.f32 %f21, %f18, 0f3F000000;
div.rn.f32 %f22, %f18, %f21;
sub.f32 %f23, %f9, %f20;
sub.f32 %f24, %f12, %f22;
tex.2d.v4.u32.f32 {%r14, %r15, %r16, %r17}, [%rd1, {%f23, %f24}];
and.b32 %r18, %r14, 255;
add.f32 %f25, %f9, %f20;
tex.2d.v4.u32.f32 {%r19, %r20, %r21, %r22}, [%rd1, {%f25, %f24}];
and.b32 %r23, %r19, 255;
add.f32 %f26, %f12, %f22;
tex.2d.v4.u32.f32 {%r24, %r25, %r26, %r27}, [%rd1, {%f23, %f26}];
and.b32 %r28, %r24, 255;
tex.2d.v4.u32.f32 {%r29, %r30, %r31, %r32}, [%rd1, {%f25, %f26}];
and.b32 %r33, %r29, 255;
add.s32 %r34, %r18, %r23;
add.s32 %r35, %r34, %r28;
add.s32 %r36, %r35, %r33;
add.s32 %r37, %r36, 2;
shr.u32 %r38, %r37, 2;
mad.lo.s32 %r39, %r2, %r5, %r1;
cvt.s64.s32 %rd3, %r39;
cvta.to.global.u64 %rd4, %rd2;
add.s64 %rd5, %rd4, %rd3;
st.global.u8 [%rd5], %r38;
BB0_2:
ret;
}
// .globl Subsample_Bilinear_uchar2
.visible .entry Subsample_Bilinear_uchar2(
.param .u64 Subsample_Bilinear_uchar2_param_0,
.param .u64 Subsample_Bilinear_uchar2_param_1,
.param .u32 Subsample_Bilinear_uchar2_param_2,
.param .u32 Subsample_Bilinear_uchar2_param_3,
.param .u32 Subsample_Bilinear_uchar2_param_4,
.param .u32 Subsample_Bilinear_uchar2_param_5,
.param .u32 Subsample_Bilinear_uchar2_param_6
)
{
.reg .pred %p<4>;
.reg .b16 %rs<3>;
.reg .f32 %f<27>;
.reg .b32 %r<49>;
.reg .b64 %rd<6>;
ld.param.u64 %rd1, [Subsample_Bilinear_uchar2_param_0];
ld.param.u64 %rd2, [Subsample_Bilinear_uchar2_param_1];
ld.param.u32 %r3, [Subsample_Bilinear_uchar2_param_2];
ld.param.u32 %r4, [Subsample_Bilinear_uchar2_param_3];
ld.param.u32 %r5, [Subsample_Bilinear_uchar2_param_4];
ld.param.u32 %r6, [Subsample_Bilinear_uchar2_param_5];
ld.param.u32 %r7, [Subsample_Bilinear_uchar2_param_6];
mov.u32 %r8, %ctaid.x;
mov.u32 %r9, %ntid.x;
mov.u32 %r10, %tid.x;
mad.lo.s32 %r1, %r9, %r8, %r10;
mov.u32 %r11, %ntid.y;
mov.u32 %r12, %ctaid.y;
mov.u32 %r13, %tid.y;
mad.lo.s32 %r2, %r11, %r12, %r13;
setp.lt.s32 %p1, %r2, %r4;
setp.lt.s32 %p2, %r1, %r3;
and.pred %p3, %p1, %p2;
@!%p3 bra BB1_2;
bra.uni BB1_1;
BB1_1:
cvt.rn.f32.s32 %f1, %r6;
cvt.rn.f32.s32 %f2, %r3;
div.rn.f32 %f3, %f1, %f2;
cvt.rn.f32.s32 %f4, %r4;
cvt.rn.f32.s32 %f5, %r7;
div.rn.f32 %f6, %f5, %f4;
cvt.rn.f32.s32 %f7, %r1;
add.f32 %f8, %f7, 0f3F000000;
mul.f32 %f9, %f8, %f3;
cvt.rn.f32.s32 %f10, %r2;
add.f32 %f11, %f10, 0f3F000000;
mul.f32 %f12, %f11, %f6;
add.f32 %f13, %f3, 0fBF800000;
mul.f32 %f14, %f13, 0f3F000000;
cvt.sat.f32.f32 %f15, %f14;
add.f32 %f16, %f6, 0fBF800000;
mul.f32 %f17, %f16, 0f3F000000;
cvt.sat.f32.f32 %f18, %f17;
add.f32 %f19, %f15, 0f3F000000;
div.rn.f32 %f20, %f15, %f19;
add.f32 %f21, %f18, 0f3F000000;
div.rn.f32 %f22, %f18, %f21;
sub.f32 %f23, %f9, %f20;
sub.f32 %f24, %f12, %f22;
tex.2d.v4.u32.f32 {%r14, %r15, %r16, %r17}, [%rd1, {%f23, %f24}];
add.f32 %f25, %f9, %f20;
tex.2d.v4.u32.f32 {%r18, %r19, %r20, %r21}, [%rd1, {%f25, %f24}];
add.f32 %f26, %f12, %f22;
tex.2d.v4.u32.f32 {%r22, %r23, %r24, %r25}, [%rd1, {%f23, %f26}];
tex.2d.v4.u32.f32 {%r26, %r27, %r28, %r29}, [%rd1, {%f25, %f26}];
and.b32 %r30, %r14, 255;
and.b32 %r31, %r18, 255;
and.b32 %r32, %r22, 255;
and.b32 %r33, %r26, 255;
add.s32 %r34, %r30, %r31;
add.s32 %r35, %r34, %r32;
add.s32 %r36, %r35, %r33;
add.s32 %r37, %r36, 2;
shr.u32 %r38, %r37, 2;
and.b32 %r39, %r15, 255;
and.b32 %r40, %r19, 255;
and.b32 %r41, %r23, 255;
and.b32 %r42, %r27, 255;
add.s32 %r43, %r39, %r40;
add.s32 %r44, %r43, %r41;
add.s32 %r45, %r44, %r42;
add.s32 %r46, %r45, 2;
shr.u32 %r47, %r46, 2;
mad.lo.s32 %r48, %r2, %r5, %r1;
cvta.to.global.u64 %rd3, %rd2;
mul.wide.s32 %rd4, %r48, 2;
add.s64 %rd5, %rd3, %rd4;
cvt.u16.u32 %rs1, %r47;
cvt.u16.u32 %rs2, %r38;
st.global.v2.u8 [%rd5], {%rs2, %rs1};
BB1_2:
ret;
}
// .globl Subsample_Bilinear_ushort
.visible .entry Subsample_Bilinear_ushort(
.param .u64 Subsample_Bilinear_ushort_param_0,
.param .u64 Subsample_Bilinear_ushort_param_1,
.param .u32 Subsample_Bilinear_ushort_param_2,
.param .u32 Subsample_Bilinear_ushort_param_3,
.param .u32 Subsample_Bilinear_ushort_param_4,
.param .u32 Subsample_Bilinear_ushort_param_5,
.param .u32 Subsample_Bilinear_ushort_param_6
)
{
.reg .pred %p<4>;
.reg .f32 %f<27>;
.reg .b32 %r<40>;
.reg .b64 %rd<6>;
ld.param.u64 %rd1, [Subsample_Bilinear_ushort_param_0];
ld.param.u64 %rd2, [Subsample_Bilinear_ushort_param_1];
ld.param.u32 %r3, [Subsample_Bilinear_ushort_param_2];
ld.param.u32 %r4, [Subsample_Bilinear_ushort_param_3];
ld.param.u32 %r5, [Subsample_Bilinear_ushort_param_4];
ld.param.u32 %r6, [Subsample_Bilinear_ushort_param_5];
ld.param.u32 %r7, [Subsample_Bilinear_ushort_param_6];
mov.u32 %r8, %ctaid.x;
mov.u32 %r9, %ntid.x;
mov.u32 %r10, %tid.x;
mad.lo.s32 %r1, %r9, %r8, %r10;
mov.u32 %r11, %ntid.y;
mov.u32 %r12, %ctaid.y;
mov.u32 %r13, %tid.y;
mad.lo.s32 %r2, %r11, %r12, %r13;
setp.lt.s32 %p1, %r2, %r4;
setp.lt.s32 %p2, %r1, %r3;
and.pred %p3, %p1, %p2;
@!%p3 bra BB2_2;
bra.uni BB2_1;
BB2_1:
cvt.rn.f32.s32 %f1, %r6;
cvt.rn.f32.s32 %f2, %r3;
div.rn.f32 %f3, %f1, %f2;
cvt.rn.f32.s32 %f4, %r4;
cvt.rn.f32.s32 %f5, %r7;
div.rn.f32 %f6, %f5, %f4;
cvt.rn.f32.s32 %f7, %r1;
add.f32 %f8, %f7, 0f3F000000;
mul.f32 %f9, %f8, %f3;
cvt.rn.f32.s32 %f10, %r2;
add.f32 %f11, %f10, 0f3F000000;
mul.f32 %f12, %f11, %f6;
add.f32 %f13, %f3, 0fBF800000;
mul.f32 %f14, %f13, 0f3F000000;
cvt.sat.f32.f32 %f15, %f14;
add.f32 %f16, %f6, 0fBF800000;
mul.f32 %f17, %f16, 0f3F000000;
cvt.sat.f32.f32 %f18, %f17;
add.f32 %f19, %f15, 0f3F000000;
div.rn.f32 %f20, %f15, %f19;
add.f32 %f21, %f18, 0f3F000000;
div.rn.f32 %f22, %f18, %f21;
sub.f32 %f23, %f9, %f20;
sub.f32 %f24, %f12, %f22;
tex.2d.v4.u32.f32 {%r14, %r15, %r16, %r17}, [%rd1, {%f23, %f24}];
and.b32 %r18, %r14, 65535;
add.f32 %f25, %f9, %f20;
tex.2d.v4.u32.f32 {%r19, %r20, %r21, %r22}, [%rd1, {%f25, %f24}];
and.b32 %r23, %r19, 65535;
add.f32 %f26, %f12, %f22;
tex.2d.v4.u32.f32 {%r24, %r25, %r26, %r27}, [%rd1, {%f23, %f26}];
and.b32 %r28, %r24, 65535;
tex.2d.v4.u32.f32 {%r29, %r30, %r31, %r32}, [%rd1, {%f25, %f26}];
and.b32 %r33, %r29, 65535;
add.s32 %r34, %r18, %r23;
add.s32 %r35, %r34, %r28;
add.s32 %r36, %r35, %r33;
add.s32 %r37, %r36, 2;
shr.u32 %r38, %r37, 2;
mad.lo.s32 %r39, %r2, %r5, %r1;
cvta.to.global.u64 %rd3, %rd2;
mul.wide.s32 %rd4, %r39, 2;
add.s64 %rd5, %rd3, %rd4;
st.global.u16 [%rd5], %r38;
BB2_2:
ret;
}
// .globl Subsample_Bilinear_ushort2
.visible .entry Subsample_Bilinear_ushort2(
.param .u64 Subsample_Bilinear_ushort2_param_0,
.param .u64 Subsample_Bilinear_ushort2_param_1,
.param .u32 Subsample_Bilinear_ushort2_param_2,
.param .u32 Subsample_Bilinear_ushort2_param_3,
.param .u32 Subsample_Bilinear_ushort2_param_4,
.param .u32 Subsample_Bilinear_ushort2_param_5,
.param .u32 Subsample_Bilinear_ushort2_param_6
)
{
.reg .pred %p<4>;
.reg .b16 %rs<3>;
.reg .f32 %f<27>;
.reg .b32 %r<49>;
.reg .b64 %rd<6>;
ld.param.u64 %rd1, [Subsample_Bilinear_ushort2_param_0];
ld.param.u64 %rd2, [Subsample_Bilinear_ushort2_param_1];
ld.param.u32 %r3, [Subsample_Bilinear_ushort2_param_2];
ld.param.u32 %r4, [Subsample_Bilinear_ushort2_param_3];
ld.param.u32 %r5, [Subsample_Bilinear_ushort2_param_4];
ld.param.u32 %r6, [Subsample_Bilinear_ushort2_param_5];
ld.param.u32 %r7, [Subsample_Bilinear_ushort2_param_6];
mov.u32 %r8, %ctaid.x;
mov.u32 %r9, %ntid.x;
mov.u32 %r10, %tid.x;
mad.lo.s32 %r1, %r9, %r8, %r10;
mov.u32 %r11, %ntid.y;
mov.u32 %r12, %ctaid.y;
mov.u32 %r13, %tid.y;
mad.lo.s32 %r2, %r11, %r12, %r13;
setp.lt.s32 %p1, %r2, %r4;
setp.lt.s32 %p2, %r1, %r3;
and.pred %p3, %p1, %p2;
@!%p3 bra BB3_2;
bra.uni BB3_1;
BB3_1:
cvt.rn.f32.s32 %f1, %r6;
cvt.rn.f32.s32 %f2, %r3;
div.rn.f32 %f3, %f1, %f2;
cvt.rn.f32.s32 %f4, %r4;
cvt.rn.f32.s32 %f5, %r7;
div.rn.f32 %f6, %f5, %f4;
cvt.rn.f32.s32 %f7, %r1;
add.f32 %f8, %f7, 0f3F000000;
mul.f32 %f9, %f8, %f3;
cvt.rn.f32.s32 %f10, %r2;
add.f32 %f11, %f10, 0f3F000000;
mul.f32 %f12, %f11, %f6;
add.f32 %f13, %f3, 0fBF800000;
mul.f32 %f14, %f13, 0f3F000000;
cvt.sat.f32.f32 %f15, %f14;
add.f32 %f16, %f6, 0fBF800000;
mul.f32 %f17, %f16, 0f3F000000;
cvt.sat.f32.f32 %f18, %f17;
add.f32 %f19, %f15, 0f3F000000;
div.rn.f32 %f20, %f15, %f19;
add.f32 %f21, %f18, 0f3F000000;
div.rn.f32 %f22, %f18, %f21;
sub.f32 %f23, %f9, %f20;
sub.f32 %f24, %f12, %f22;
tex.2d.v4.u32.f32 {%r14, %r15, %r16, %r17}, [%rd1, {%f23, %f24}];
add.f32 %f25, %f9, %f20;
tex.2d.v4.u32.f32 {%r18, %r19, %r20, %r21}, [%rd1, {%f25, %f24}];
add.f32 %f26, %f12, %f22;
tex.2d.v4.u32.f32 {%r22, %r23, %r24, %r25}, [%rd1, {%f23, %f26}];
tex.2d.v4.u32.f32 {%r26, %r27, %r28, %r29}, [%rd1, {%f25, %f26}];
and.b32 %r30, %r14, 65535;
and.b32 %r31, %r18, 65535;
and.b32 %r32, %r22, 65535;
and.b32 %r33, %r26, 65535;
add.s32 %r34, %r30, %r31;
add.s32 %r35, %r34, %r32;
add.s32 %r36, %r35, %r33;
add.s32 %r37, %r36, 2;
shr.u32 %r38, %r37, 2;
and.b32 %r39, %r15, 65535;
and.b32 %r40, %r19, 65535;
and.b32 %r41, %r23, 65535;
and.b32 %r42, %r27, 65535;
add.s32 %r43, %r39, %r40;
add.s32 %r44, %r43, %r41;
add.s32 %r45, %r44, %r42;
add.s32 %r46, %r45, 2;
shr.u32 %r47, %r46, 2;
mad.lo.s32 %r48, %r2, %r5, %r1;
cvta.to.global.u64 %rd3, %rd2;
mul.wide.s32 %rd4, %r48, 4;
add.s64 %rd5, %rd3, %rd4;
cvt.u16.u32 %rs1, %r47;
cvt.u16.u32 %rs2, %r38;
st.global.v2.u16 [%rd5], {%rs2, %rs1};
BB3_2:
ret;
}
//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-19856038
// Cuda compilation tools, release 7.5, V7.5.17
// Based on LLVM 3.4svn
//
.version 4.3
.target sm_20
.address_size 64
// .globl uyvy2nv12
.visible .entry uyvy2nv12(
.param .u64 uyvy2nv12_param_0,
.param .u64 uyvy2nv12_param_1,
.param .u64 uyvy2nv12_param_2,
.param .u64 uyvy2nv12_param_3,
.param .u32 uyvy2nv12_param_4,
.param .u32 uyvy2nv12_param_5
)
{
.reg .pred %p<4>;
.reg .b16 %rs<5>;
.reg .b32 %r<28>;
.reg .b64 %rd<30>;
ld.param.u64 %rd1, [uyvy2nv12_param_0];
ld.param.u64 %rd2, [uyvy2nv12_param_1];
ld.param.u64 %rd3, [uyvy2nv12_param_2];
ld.param.u64 %rd4, [uyvy2nv12_param_3];
ld.param.u32 %r5, [uyvy2nv12_param_4];
ld.param.u32 %r4, [uyvy2nv12_param_5];
mov.u32 %r6, %ctaid.x;
mov.u32 %r7, %ntid.x;
mov.u32 %r8, %tid.x;
mad.lo.s32 %r1, %r6, %r7, %r8;
shl.b32 %r2, %r1, 1;
mov.u32 %r9, %ctaid.y;
mov.u32 %r10, %ntid.y;
mov.u32 %r11, %tid.y;
mad.lo.s32 %r12, %r9, %r10, %r11;
shl.b32 %r3, %r12, 1;
add.s32 %r13, %r2, 2;
setp.gt.u32 %p1, %r13, %r5;
add.s32 %r14, %r3, 2;
setp.gt.u32 %p2, %r14, %r4;
or.pred %p3, %p1, %p2;
@%p3 bra BB0_2;
cvta.to.global.u64 %rd5, %rd3;
cvta.to.global.u64 %rd6, %rd1;
cvt.u64.u32 %rd7, %r4;
mul.lo.s64 %rd8, %rd7, %rd4;
cvt.s64.s32 %rd9, %r3;
mul.lo.s64 %rd10, %rd9, %rd2;
shl.b32 %r15, %r1, 2;
cvt.s64.s32 %rd11, %r15;
add.s64 %rd12, %rd10, %rd11;
add.s64 %rd13, %rd6, %rd12;
ld.global.u8 %rs1, [%rd13+1];
ld.global.u8 %rs2, [%rd13+3];
add.s32 %r16, %r3, 1;
cvt.s64.s32 %rd14, %r16;
mul.lo.s64 %rd15, %rd14, %rd2;
add.s64 %rd16, %rd15, %rd11;
add.s64 %rd17, %rd6, %rd16;
ld.global.u8 %rs3, [%rd17+1];
ld.global.u8 %rs4, [%rd17+3];
mul.lo.s64 %rd18, %rd9, %rd4;
cvt.s64.s32 %rd19, %r2;
add.s64 %rd20, %rd18, %rd19;
add.s64 %rd21, %rd5, %rd20;
ld.global.u8 %r17, [%rd13];
ld.global.u8 %r18, [%rd17];
ld.global.u8 %r19, [%rd13+2];
ld.global.u8 %r20, [%rd17+2];
st.global.u8 [%rd21], %rs1;
st.global.u8 [%rd21+1], %rs2;
mul.lo.s64 %rd22, %rd14, %rd4;
add.s64 %rd23, %rd22, %rd19;
add.s64 %rd24, %rd5, %rd23;
st.global.u8 [%rd24], %rs3;
st.global.u8 [%rd24+1], %rs4;
add.s32 %r21, %r18, %r17;
shr.u32 %r22, %r21, 1;
shr.u32 %r23, %r3, 31;
add.s32 %r24, %r3, %r23;
shr.s32 %r25, %r24, 1;
cvt.s64.s32 %rd25, %r25;
mul.lo.s64 %rd26, %rd25, %rd4;
add.s64 %rd27, %rd26, %rd19;
add.s64 %rd28, %rd27, %rd8;
add.s64 %rd29, %rd5, %rd28;
st.global.u8 [%rd29], %r22;
add.s32 %r26, %r20, %r19;
shr.u32 %r27, %r26, 1;
st.global.u8 [%rd29+1], %r27;
BB0_2:
ret;
}
// .globl argb_nv12
.visible .entry argb_nv12(
.param .u64 argb_nv12_param_0,
.param .u64 argb_nv12_param_1,
.param .u64 argb_nv12_param_2,
.param .u64 argb_nv12_param_3,
.param .u32 argb_nv12_param_4,
.param .u32 argb_nv12_param_5
)
{
.reg .pred %p<6>;
.reg .b16 %rs<13>;
.reg .b32 %r<125>;
.reg .b64 %rd<28>;
ld.param.u64 %rd1, [argb_nv12_param_0];
ld.param.u64 %rd2, [argb_nv12_param_1];
ld.param.u64 %rd3, [argb_nv12_param_2];
ld.param.u64 %rd4, [argb_nv12_param_3];
ld.param.u32 %r5, [argb_nv12_param_4];
ld.param.u32 %r4, [argb_nv12_param_5];
mov.u32 %r6, %ctaid.x;
mov.u32 %r7, %ntid.x;
mov.u32 %r8, %tid.x;
mad.lo.s32 %r1, %r6, %r7, %r8;
shl.b32 %r2, %r1, 1;
mov.u32 %r9, %ctaid.y;
mov.u32 %r10, %ntid.y;
mov.u32 %r11, %tid.y;
mad.lo.s32 %r12, %r9, %r10, %r11;
or.b32 %r13, %r12, %r1;
shl.b32 %r3, %r12, 1;
setp.gt.u32 %p1, %r2, %r5;
setp.gt.u32 %p2, %r3, %r4;
or.pred %p3, %p1, %p2;
shl.b32 %r14, %r13, 1;
setp.lt.s32 %p4, %r14, 0;
or.pred %p5, %p3, %p4;
@%p5 bra BB1_2;
cvta.to.global.u64 %rd5, %rd3;
cvta.to.global.u64 %rd6, %rd1;
shl.b32 %r15, %r1, 3;
cvt.s64.s32 %rd7, %r15;
cvt.s64.s32 %rd8, %r3;
mul.lo.s64 %rd9, %rd8, %rd2;
add.s64 %rd10, %rd9, %rd7;
add.s32 %r16, %r3, 1;
cvt.s64.s32 %rd11, %r16;
mul.lo.s64 %rd12, %rd11, %rd2;
add.s64 %rd13, %rd12, %rd7;
mul.lo.s64 %rd14, %rd8, %rd4;
cvt.s64.s32 %rd15, %r2;
add.s64 %rd16, %rd14, %rd15;
add.s64 %rd17, %rd5, %rd16;
add.s64 %rd18, %rd16, %rd4;
add.s64 %rd19, %rd5, %rd18;
add.s64 %rd20, %rd6, %rd10;
ld.global.u8 %rs1, [%rd20+1];
mul.wide.u16 %r17, %rs1, 66;
ld.global.u8 %rs2, [%rd20+2];
mul.wide.u16 %r18, %rs2, 129;
ld.global.u8 %r19, [%rd20+3];
add.s32 %r20, %r17, %r18;
add.s32 %r21, %r20, 128;
mad.lo.s32 %r22, %r19, 25, %r21;
shr.u32 %r23, %r22, 8;
add.s32 %r24, %r23, 16;
st.global.u8 [%rd17], %r24;
ld.global.u8 %rs3, [%rd20+5];
mul.wide.u16 %r25, %rs3, 66;
ld.global.u8 %rs4, [%rd20+6];
mul.wide.u16 %r26, %rs4, 129;
ld.global.u8 %r27, [%rd20+7];
add.s32 %r28, %r25, %r26;
add.s32 %r29, %r28, 128;
mad.lo.s32 %r30, %r27, 25, %r29;
shr.u32 %r31, %r30, 8;
add.s32 %r32, %r31, 16;
st.global.u8 [%rd17+1], %r32;
add.s64 %rd21, %rd6, %rd13;
ld.global.u8 %rs5, [%rd21+1];
mul.wide.u16 %r33, %rs5, 66;
ld.global.u8 %rs6, [%rd21+2];
mul.wide.u16 %r34, %rs6, 129;
ld.global.u8 %r35, [%rd21+3];
add.s32 %r36, %r33, %r34;
add.s32 %r37, %r36, 128;
mad.lo.s32 %r38, %r35, 25, %r37;
shr.u32 %r39, %r38, 8;
add.s32 %r40, %r39, 16;
st.global.u8 [%rd19], %r40;
ld.global.u8 %rs7, [%rd21+5];
mul.wide.u16 %r41, %rs7, 66;
ld.global.u8 %rs8, [%rd21+6];
mul.wide.u16 %r42, %rs8, 129;
ld.global.u8 %r43, [%rd21+7];
add.s32 %r44, %r41, %r42;
add.s32 %r45, %r44, 128;
mad.lo.s32 %r46, %r43, 25, %r45;
shr.u32 %r47, %r46, 8;
add.s32 %r48, %r47, 16;
st.global.u8 [%rd19+1], %r48;
cvt.u64.u32 %rd22, %r4;
mul.lo.s64 %rd23, %rd22, %rd4;
shr.u64 %rd24, %rd14, 1;
add.s64 %rd25, %rd15, %rd23;
add.s64 %rd26, %rd25, %rd24;
add.s64 %rd27, %rd5, %rd26;
ld.global.u8 %rs9, [%rd20+1];
cvt.u32.u16 %r49, %rs9;
ld.global.u8 %r50, [%rd20+2];
mul.lo.s32 %r51, %r50, -74;
ld.global.u8 %r52, [%rd20+3];
mad.lo.s32 %r53, %r49, -38, %r51;
add.s32 %r54, %r53, 128;
mad.lo.s32 %r55, %r52, 112, %r54;
shr.u32 %r56, %r55, 8;
add.s32 %r57, %r56, 128;
and.b32 %r58, %r57, 255;
ld.global.u8 %rs10, [%rd20+5];
cvt.u32.u16 %r59, %rs10;
ld.global.u8 %r60, [%rd20+6];
mul.lo.s32 %r61, %r60, -74;
ld.global.u8 %r62, [%rd20+7];
mad.lo.s32 %r63, %r59, -38, %r61;
add.s32 %r64, %r63, 128;
mad.lo.s32 %r65, %r62, 112, %r64;
shr.u32 %r66, %r65, 8;
add.s32 %r67, %r66, 128;
and.b32 %r68, %r67, 255;
add.s32 %r69, %r68, %r58;
ld.global.u8 %rs11, [%rd21+1];
cvt.u32.u16 %r70, %rs11;
ld.global.u8 %r71, [%rd21+2];
mul.lo.s32 %r72, %r71, -74;
ld.global.u8 %r73, [%rd21+3];
mad.lo.s32 %r74, %r70, -38, %r72;
add.s32 %r75, %r74, 128;
mad.lo.s32 %r76, %r73, 112, %r75;
shr.u32 %r77, %r76, 8;
add.s32 %r78, %r77, 128;
and.b32 %r79, %r78, 255;
add.s32 %r80, %r69, %r79;
ld.global.u8 %rs12, [%rd21+5];
cvt.u32.u16 %r81, %rs12;
ld.global.u8 %r82, [%rd21+6];
mul.lo.s32 %r83, %r82, -74;
ld.global.u8 %r84, [%rd21+7];
mad.lo.s32 %r85, %r81, -38, %r83;
add.s32 %r86, %r85, 128;
mad.lo.s32 %r87, %r84, 112, %r86;
shr.u32 %r88, %r87, 8;
add.s32 %r89, %r88, 128;
and.b32 %r90, %r89, 255;
add.s32 %r91, %r80, %r90;
shr.u32 %r92, %r91, 2;
mul.wide.u16 %r93, %rs9, 112;
mad.lo.s32 %r94, %r50, -94, %r93;
add.s32 %r95, %r94, 128;
mad.lo.s32 %r96, %r52, -18, %r95;
shr.u32 %r97, %r96, 8;
add.s32 %r98, %r97, 128;
and.b32 %r99, %r98, 255;
mul.wide.u16 %r100, %rs10, 112;
mad.lo.s32 %r101, %r60, -94, %r100;
add.s32 %r102, %r101, 128;
mad.lo.s32 %r103, %r62, -18, %r102;
shr.u32 %r104, %r103, 8;
add.s32 %r105, %r104, 128;
and.b32 %r106, %r105, 255;
add.s32 %r107, %r106, %r99;
mul.wide.u16 %r108, %rs11, 112;
mad.lo.s32 %r109, %r71, -94, %r108;
add.s32 %r110, %r109, 128;
mad.lo.s32 %r111, %r73, -18, %r110;
shr.u32 %r112, %r111, 8;
add.s32 %r113, %r112, 128;
and.b32 %r114, %r113, 255;
add.s32 %r115, %r107, %r114;
mul.wide.u16 %r116, %rs12, 112;
mad.lo.s32 %r117, %r82, -94, %r116;
add.s32 %r118, %r117, 128;
mad.lo.s32 %r119, %r84, -18, %r118;
shr.u32 %r120, %r119, 8;
add.s32 %r121, %r120, 128;
and.b32 %r122, %r121, 255;
add.s32 %r123, %r115, %r122;
shr.u32 %r124, %r123, 2;
st.global.u8 [%rd27], %r92;
st.global.u8 [%rd27+1], %r124;
BB1_2:
ret;
}
// .globl v210_nv12
.visible .entry v210_nv12(
.param .u64 v210_nv12_param_0,
.param .u64 v210_nv12_param_1,
.param .u64 v210_nv12_param_2,
.param .u64 v210_nv12_param_3,
.param .u32 v210_nv12_param_4,
.param .u32 v210_nv12_param_5
)
{
.reg .pred %p<11>;
.reg .b16 %rs<9>;
.reg .b32 %r<269>;
.reg .b64 %rd<98>;
ld.param.u64 %rd3, [v210_nv12_param_0];
ld.param.u64 %rd4, [v210_nv12_param_1];
ld.param.u64 %rd5, [v210_nv12_param_2];
ld.param.u64 %rd6, [v210_nv12_param_3];
ld.param.u32 %r10, [v210_nv12_param_4];
ld.param.u32 %r11, [v210_nv12_param_5];
mov.u32 %r12, %ctaid.x;
mov.u32 %r13, %ntid.x;
mov.u32 %r14, %tid.x;
mad.lo.s32 %r1, %r12, %r13, %r14;
shl.b32 %r2, %r1, 4;
mov.u32 %r15, %ctaid.y;
mov.u32 %r16, %ntid.y;
mov.u32 %r17, %tid.y;
mad.lo.s32 %r18, %r15, %r16, %r17;
shl.b32 %r3, %r18, 1;
setp.ge.u32 %p1, %r3, %r11;
@%p1 bra BB2_14;
add.s32 %r19, %r10, 47;
mul.wide.u32 %rd7, %r19, -1431655765;
shr.u64 %rd8, %rd7, 32;
cvt.u32.u64 %r20, %rd8;
shl.b32 %r21, %r20, 2;
and.b32 %r22, %r21, -128;
add.s32 %r23, %r3, 2;
setp.le.u32 %p2, %r23, %r11;
add.s32 %r24, %r2, 16;
setp.le.s32 %p3, %r24, %r22;
and.pred %p4, %p2, %p3;
@!%p4 bra BB2_14;
bra.uni BB2_2;
BB2_2:
cvta.to.global.u64 %rd9, %rd3;
mul.lo.s32 %r25, %r1, 6;
cvt.s64.s32 %rd10, %r3;
mul.lo.s64 %rd11, %rd10, %rd4;
cvt.s64.s32 %rd12, %r2;
add.s64 %rd13, %rd11, %rd12;
add.s64 %rd1, %rd9, %rd13;
add.s32 %r26, %r3, 1;
cvt.s64.s32 %rd14, %r26;
mul.lo.s64 %rd15, %rd14, %rd4;
add.s64 %rd16, %rd15, %rd12;
add.s64 %rd2, %rd9, %rd16;
ld.global.u8 %r27, [%rd1+4];
ld.global.u8 %rs1, [%rd1+5];
mul.wide.u16 %r28, %rs1, 256;
add.s32 %r29, %r28, %r27;
ld.global.u8 %r30, [%rd1+6];
shl.b32 %r31, %r30, 16;
add.s32 %r32, %r29, %r31;
ld.global.u8 %r33, [%rd1+7];
shl.b32 %r34, %r33, 24;
add.s32 %r4, %r32, %r34;
ld.global.u8 %r35, [%rd1+8];
ld.global.u8 %rs2, [%rd1+9];
mul.wide.u16 %r36, %rs2, 256;
add.s32 %r37, %r36, %r35;
ld.global.u8 %r38, [%rd1+10];
shl.b32 %r39, %r38, 16;
add.s32 %r40, %r37, %r39;
ld.global.u8 %r41, [%rd1+11];
shl.b32 %r42, %r41, 24;
add.s32 %r5, %r40, %r42;
ld.global.u8 %r43, [%rd1+12];
ld.global.u8 %rs3, [%rd1+13];
mul.wide.u16 %r44, %rs3, 256;
add.s32 %r45, %r44, %r43;
ld.global.u8 %r46, [%rd1+14];
shl.b32 %r47, %r46, 16;
add.s32 %r48, %r45, %r47;
ld.global.u8 %r49, [%rd1+15];
shl.b32 %r50, %r49, 24;
add.s32 %r6, %r48, %r50;
ld.global.u8 %r51, [%rd2+4];
ld.global.u8 %rs4, [%rd2+5];
mul.wide.u16 %r52, %rs4, 256;
add.s32 %r53, %r52, %r51;
ld.global.u8 %r54, [%rd2+6];
shl.b32 %r55, %r54, 16;
add.s32 %r56, %r53, %r55;
ld.global.u8 %r57, [%rd2+7];
shl.b32 %r58, %r57, 24;
add.s32 %r7, %r56, %r58;
ld.global.u8 %r59, [%rd2+8];
ld.global.u8 %rs5, [%rd2+9];
mul.wide.u16 %r60, %rs5, 256;
add.s32 %r61, %r60, %r59;
ld.global.u8 %r62, [%rd2+10];
shl.b32 %r63, %r62, 16;
add.s32 %r64, %r61, %r63;
ld.global.u8 %r65, [%rd2+11];
shl.b32 %r66, %r65, 24;
add.s32 %r8, %r64, %r66;
ld.global.u8 %r67, [%rd2+12];
ld.global.u8 %rs6, [%rd2+13];
mul.wide.u16 %r68, %rs6, 256;
add.s32 %r69, %r68, %r67;
ld.global.u8 %r70, [%rd2+14];
shl.b32 %r71, %r70, 16;
add.s32 %r72, %r69, %r71;
ld.global.u8 %r73, [%rd2+15];
shl.b32 %r74, %r73, 24;
add.s32 %r9, %r72, %r74;
setp.ge.u32 %p5, %r25, %r10;
@%p5 bra BB2_4;
ld.global.u8 %r75, [%rd1];
ld.global.u8 %rs7, [%rd1+1];
mul.wide.u16 %r76, %rs7, 256;
add.s32 %r77, %r76, %r75;
ld.global.u8 %r78, [%rd1+2];
shl.b32 %r79, %r78, 16;
add.s32 %r80, %r77, %r79;
ld.global.u8 %r81, [%rd1+3];
shl.b32 %r82, %r81, 24;
ld.global.u8 %r83, [%rd2];
ld.global.u8 %rs8, [%rd2+1];
mul.wide.u16 %r84, %rs8, 256;
add.s32 %r85, %r84, %r83;
ld.global.u8 %r86, [%rd2+2];
shl.b32 %r87, %r86, 16;
add.s32 %r88, %r85, %r87;
ld.global.u8 %r89, [%rd2+3];
shl.b32 %r90, %r89, 24;
add.s32 %r91, %r88, %r90;
shr.u32 %r92, %r91, 10;
add.s32 %r93, %r80, %r82;
shr.u32 %r94, %r93, 10;
add.s32 %r95, %r92, 2;
shr.u32 %r96, %r91, 20;
add.s32 %r97, %r94, 2;
shr.u32 %r98, %r93, 20;
add.s32 %r99, %r96, 2;
shr.u32 %r100, %r95, 2;
add.s32 %r101, %r98, 2;
shr.u32 %r102, %r97, 2;
add.s32 %r103, %r91, 2;
add.s32 %r104, %r93, 2;
mul.lo.s64 %rd18, %rd10, %rd6;
cvt.s64.s32 %rd19, %r25;
add.s64 %rd20, %rd18, %rd19;
cvta.to.global.u64 %rd21, %rd5;
add.s64 %rd22, %rd21, %rd20;
st.global.u8 [%rd22], %r102;
mul.lo.s64 %rd24, %rd14, %rd6;
add.s64 %rd25, %rd24, %rd19;
add.s64 %rd26, %rd21, %rd25;
st.global.u8 [%rd26], %r100;
bfe.u32 %r116, %r104, 2, 8;
bfe.u32 %r117, %r103, 2, 8;
add.s32 %r118, %r117, %r116;
shr.u32 %r119, %r118, 1;
bfe.u32 %r120, %r18, 30, 1;
add.s32 %r121, %r3, %r120;
shr.s32 %r122, %r121, 1;
cvt.s64.s32 %rd27, %r122;
mul.lo.s64 %rd28, %rd27, %rd6;
add.s64 %rd29, %rd28, %rd19;
cvt.u64.u32 %rd30, %r11;
mul.lo.s64 %rd31, %rd30, %rd6;
add.s64 %rd32, %rd29, %rd31;
add.s64 %rd33, %rd21, %rd32;
st.global.u8 [%rd33], %r119;
bfe.u32 %r123, %r101, 2, 8;
bfe.u32 %r124, %r99, 2, 8;
add.s32 %r125, %r124, %r123;
shr.u32 %r126, %r125, 1;
st.global.u8 [%rd33+1], %r126;
BB2_4:
mad.lo.s32 %r131, %r1, 6, 1;
setp.ge.u32 %p6, %r131, %r10;
@%p6 bra BB2_6;
add.s32 %r132, %r4, 2;
shr.u32 %r133, %r132, 2;
add.s32 %r134, %r7, 2;
shr.u32 %r135, %r134, 2;
mul.lo.s64 %rd35, %rd10, %rd6;
cvt.s64.s32 %rd36, %r25;
add.s64 %rd37, %rd35, %rd36;
cvta.to.global.u64 %rd38, %rd5;
add.s64 %rd39, %rd38, %rd37;
st.global.u8 [%rd39+1], %r133;
mul.lo.s64 %rd41, %rd14, %rd6;
add.s64 %rd42, %rd41, %rd36;
add.s64 %rd43, %rd38, %rd42;
st.global.u8 [%rd43+1], %r135;
BB2_6:
mad.lo.s32 %r151, %r1, 6, 2;
setp.ge.u32 %p7, %r151, %r10;
@%p7 bra BB2_8;
shr.u32 %r152, %r4, 20;
shr.u32 %r153, %r4, 10;
add.s32 %r154, %r152, 2;
shr.u32 %r155, %r154, 2;
add.s32 %r156, %r5, 2;
add.s32 %r157, %r153, 2;
shr.u32 %r158, %r7, 20;
shr.u32 %r159, %r7, 10;
add.s32 %r160, %r158, 2;
shr.u32 %r161, %r160, 2;
add.s32 %r162, %r8, 2;
add.s32 %r163, %r159, 2;
cvt.s64.s32 %rd44, %r25;
mul.lo.s64 %rd46, %rd10, %rd6;
add.s64 %rd47, %rd46, %rd44;
cvta.to.global.u64 %rd48, %rd5;
bfe.u32 %r174, %r18, 30, 1;
add.s32 %r175, %r3, %r174;
shr.s32 %r176, %r175, 1;
cvt.s64.s32 %rd49, %r176;
mul.lo.s64 %rd50, %rd49, %rd6;
add.s64 %rd51, %rd50, %rd44;
cvt.u64.u32 %rd52, %r11;
mul.lo.s64 %rd53, %rd52, %rd6;
add.s64 %rd54, %rd53, %rd51;
add.s64 %rd55, %rd54, %rd48;
add.s64 %rd56, %rd48, %rd47;
st.global.u8 [%rd56+2], %r155;
mul.lo.s64 %rd58, %rd14, %rd6;
add.s64 %rd59, %rd58, %rd44;
add.s64 %rd60, %rd48, %rd59;
st.global.u8 [%rd60+2], %r161;
bfe.u32 %r178, %r163, 2, 8;
bfe.u32 %r179, %r157, 2, 8;
add.s32 %r180, %r178, %r179;
shr.u32 %r181, %r180, 1;
st.global.u8 [%rd55+2], %r181;
bfe.u32 %r182, %r162, 2, 8;
bfe.u32 %r183, %r156, 2, 8;
add.s32 %r184, %r182, %r183;
shr.u32 %r185, %r184, 1;
st.global.u8 [%rd55+3], %r185;
BB2_8:
mad.lo.s32 %r190, %r1, 6, 3;
setp.ge.u32 %p8, %r190, %r10;
@%p8 bra BB2_10;
shr.u32 %r191, %r5, 10;
add.s32 %r192, %r191, 2;
shr.u32 %r193, %r192, 2;
shr.u32 %r194, %r8, 10;
add.s32 %r195, %r194, 2;
shr.u32 %r196, %r195, 2;
mul.lo.s64 %rd62, %rd10, %rd6;
cvt.s64.s32 %rd63, %r25;
add.s64 %rd64, %rd62, %rd63;
cvta.to.global.u64 %rd65, %rd5;
add.s64 %rd66, %rd65, %rd64;
st.global.u8 [%rd66+3], %r193;
mul.lo.s64 %rd68, %rd14, %rd6;
add.s64 %rd69, %rd68, %rd63;
add.s64 %rd70, %rd65, %rd69;
st.global.u8 [%rd70+3], %r196;
BB2_10:
mad.lo.s32 %r212, %r1, 6, 4;
setp.ge.u32 %p9, %r212, %r10;
@%p9 bra BB2_12;
shr.u32 %r213, %r5, 20;
shr.u32 %r214, %r6, 10;
add.s32 %r215, %r6, 2;
shr.u32 %r216, %r215, 2;
add.s32 %r217, %r214, 2;
add.s32 %r218, %r213, 2;
shr.u32 %r219, %r8, 20;
shr.u32 %r220, %r9, 10;
add.s32 %r221, %r9, 2;
shr.u32 %r222, %r221, 2;
add.s32 %r223, %r220, 2;
add.s32 %r224, %r219, 2;
cvt.s64.s32 %rd71, %r25;
mul.lo.s64 %rd73, %rd10, %rd6;
add.s64 %rd74, %rd73, %rd71;
cvta.to.global.u64 %rd75, %rd5;
bfe.u32 %r235, %r18, 30, 1;
add.s32 %r236, %r3, %r235;
shr.s32 %r237, %r236, 1;
cvt.s64.s32 %rd76, %r237;
mul.lo.s64 %rd77, %rd76, %rd6;
add.s64 %rd78, %rd77, %rd71;
cvt.u64.u32 %rd79, %r11;
mul.lo.s64 %rd80, %rd79, %rd6;
add.s64 %rd81, %rd80, %rd78;
add.s64 %rd82, %rd81, %rd75;
add.s64 %rd83, %rd75, %rd74;
st.global.u8 [%rd83+4], %r216;
mul.lo.s64 %rd85, %rd14, %rd6;
add.s64 %rd86, %rd85, %rd71;
add.s64 %rd87, %rd75, %rd86;
st.global.u8 [%rd87+4], %r222;
bfe.u32 %r239, %r224, 2, 8;
bfe.u32 %r240, %r218, 2, 8;
add.s32 %r241, %r239, %r240;
shr.u32 %r242, %r241, 1;
st.global.u8 [%rd82+4], %r242;
bfe.u32 %r243, %r223, 2, 8;
bfe.u32 %r244, %r217, 2, 8;
add.s32 %r245, %r243, %r244;
shr.u32 %r246, %r245, 1;
st.global.u8 [%rd82+5], %r246;
BB2_12:
mad.lo.s32 %r251, %r1, 6, 5;
setp.ge.u32 %p10, %r251, %r10;
@%p10 bra BB2_14;
shr.u32 %r252, %r6, 20;
add.s32 %r253, %r252, 2;
shr.u32 %r254, %r253, 2;
shr.u32 %r255, %r9, 20;
add.s32 %r256, %r255, 2;
shr.u32 %r257, %r256, 2;
mul.lo.s64 %rd89, %rd10, %rd6;
cvt.s64.s32 %rd90, %r25;
add.s64 %rd91, %rd89, %rd90;
cvta.to.global.u64 %rd92, %rd5;
add.s64 %rd93, %rd92, %rd91;
st.global.u8 [%rd93+5], %r254;
mul.lo.s64 %rd95, %rd14, %rd6;
add.s64 %rd96, %rd95, %rd90;
add.s64 %rd97, %rd92, %rd96;
st.global.u8 [%rd97+5], %r257;
BB2_14:
ret;
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